Texas Instruments Corporation

Kla Tencor Corporation

Somit Joshi

Stephan Grunow

Satyavolu Srinivas Papa Rao

Kenneth D Brennan

Darius Lammont Crenshaw

Gregory Boyd Shinn

Phillip D Matz

Joe G Tran

Sameer Kumar Ajmera

Shawn T Walsh

Wayne A Bather

Michelle L Hartsell

James B Friedmann

Ju-Ai Ruan

Troy A Yocum

Jaideep Mavoori

Montray Leavy

John E Campbell

Arun Sivasothy

Rohan Gosain

Yuri E Solomentsev

Michael J McGranaghan

Janice D Makos

Various embodiments for generating a defect sample for electron beam review are provided. One method includes combining, on a defect-by-defect basis, one or more first attributes for defects determined by optical inspection of a wafer on which the defects were detected with one or more second attributes for the defects determined by optical review of the wafer thereby generating combined attributes for the defects. The method also includes separating the defects into bins based on the combined attributes for the defects. The bins correspond to different defect classifications. In addition, the method includes sampling one or more of the defects for the electron beam review based on the bins into which the defects have been separated thereby generating a defect review sample for the electron beam review.

Defect sampling for electron beam review based on defect attributes from optical inspection and optical review

The formation of a MIM (metal insulator metal) capacitor () and concurrent formation of a resistor () is disclosed. A copper diffusion barrier () is formed over a copper deposition () that serves as a bottom electrode () of the capacitor (). The copper diffusion barrier () mitigates unwanted diffusion of copper from the copper deposition (), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface () of the deposition of copper/bottom electrode. Subsequently, layers of dielectric () and conductive () materials are applied to form a dielectric () and top electrode () of the MIM capacitor (), respectively, where the layer of conductive top electrode material () also functions to concurrently develop the resistor () on the same chip as the capacitor ().

Single mask MIM capacitor and resistor with in trench copper drift barrier

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

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Sunnyvale, CA, United States of America

Somit Joshi