Kepler Computing Inc.

Eugenus, Inc.

Somilkumar J Rathi

Niloy Mukherjee

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Noriyuki Sato

Tanay Gosavi

Mauricio Manfrini

Pratyush Pandey

Jason Y Wu

Rafael Rios

Bunsen B Nie

Hae Young Kim

James David Clarkson

Sung-Hoon Jung

Nariman Naghibolashrafi

Yoshikazu Okuyama

Ramamoorthy Ramesh

Gabriel Antonio Paulius Velarde

Zeying Ren

Fnu Atiquzzaman

Jerry Mack

Jae Seok Heo

Debo Olaosebikan

Abel Fernandez

Moonsig Joo

Kyu Jin Choi

Hee Seok Kim

Srishti Chugh

M Ziaul Karim

Vinayak Veer Vats

Alex Finkelman

Bo Seon Choi

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding

The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.

Smooth titanium nitride layers and methods of forming the same

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Gate coupled non-linear polar material based capacitors for memory and logic

The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.

Titanium silicon nitride barrier layer

Methods of fabricating planar capacitors on a shared plate electrode

Capacitor devices with shared electrode and methods of fabrication

Drain coupled non-linear polar material based capacitors for memory and logic

Methods of fabricating trench capacitors on a shared plate electrode

Integration of 2T-C for memory and logic applications

Planar capacitors with shared electrode and methods of fabrication

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

Stacked capacitors with shared electrodes and methods of fabrication

The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN). In one aspect, a method of forming a thin film comprising TiN comprises exposing a semiconductor substrate to one or more first cyclical vapor deposition cycles each comprising an exposure to a first Ti precursor and an exposure to a first N precursor to form a first portion of the thin film and exposing the semiconductor substrate to one or more second cyclical vapor deposition cycles each comprising an exposure to a second Ti precursor and an exposure to a second N precursor to form a second portion of the thin film, wherein exposures to one or both of the first Ti precursor and the first N precursor during the one or more first cyclical vapor deposition cycles are at different pressures relative to corresponding exposures to one or both of the second Ti precursor and the second N precursor during the one or more second cyclical vapor deposition cycles. Aspects are also directed to semiconductor structures incorporating the thin film and method of forming the same.

Conformal and smooth titanium nitride layers and methods of forming the same

Method of fabricating transistors and stacked planar capacitors for memory and logic applications

Capacitor integrated with a transistor for logic and memory applications

Trench capacitors with shared electrode

Growing community of inventors

San Jose, CA, United States of America

Somilkumar J Rathi