Microsoft Technology Licensing, LLC

Somesh Chaturmohta

Daniel Max Firestone

Sambhrama Madhusudhan Mundkur

Norman C Lam

Alec Kochevar-Cureton

Andrew Richard Putnam

Fengfen Liu

Irena Atov

Rui Liang

Sharad Agarwal

Ryan Andrew Beckett

Gary Randall Ratterree

Rodrigo Fonseca

Michael Markovitch

Chuanji Zhang

Mark A Kasten

Venkata Praneeth Naidu Sanapathi

Scott W Hanberg

Alireza Khoshgoftarmonfared

Gaurav Thareja

The present application relates to a system for ingress traffic management. The system includes a collection system within a network configured to collect traffic arrival information for peering links of the network. The system includes a training system configured to train a model based on the traffic arrival information to predict a probability of a traffic flow arriving on a peering link. The system includes a congestion mitigation system configured to predict based on the model, for traffic flows arriving on one or more peering links, other peering links to which the traffic flows would be shifted due to a condition affecting the one or more peering links. The congestion mitigation system may determine, in response to the condition, a set of prefixes to withdraw based on the other peering links to which traffic would be shifted.

Method and system to predict the ingress interface of internet traffic

Failover functionality is by identifying at least two network paths for a media communications session between a virtual machine at a computing environment and a client application. Unique Internet Protocol (IP) addresses are assigned for the at least two network paths. Based on application and network metrics at the computing environment, a network condition at the computing environment is determined that is indicative of a performance degradation of the media communications session. A signal is communicated to the client service indicating a switch to a second path of the at least two network paths and a second of the unique IP addresses.

Convergence for time sensitive cloud applications

Techniques are disclosed for implementing direct memory access in a virtualized computing environment. A memory access policy of the virtualized computing environment is applied to a direct memory access connection request received from a first virtual machine via an exception path. The request is flagged to indicate that the request has been processed and the request is forwarded to a network interface device configured to execute offloaded network functions for one or more virtual machines. A memory access policy of the virtualized computing environment is applied to a direct memory access connection reply received from a second virtual machine on the exception path. The reply is flagged to indicate that the reply has been processed and the reply is forwarded to the network interface device. A direct memory access connection is established between first and second virtual machines in accordance with the request.

RDMA with virtual address space

A route anomaly detection and remediation system analyzes a prefix for each route received to validate the route. A route monitoring component provides a centralized querying system for all routers from all devices to study routing history. A route collection component receives and stores all routes from multiple routers at a server. A set of microservice analysis components performs prefix analysis on each received route. Each microservice analysis component analyzes one or more portions of the prefix for each route to detect hijacked routes, leaked routes, withdrawn routes and/or other unhealthy routes before the routes are utilized for routing traffic on the network. The analysis performs new prefix validation and identifies healthy routes. Alerts identifying invalid routes are transmitted to an incident management system. Healthy routes are approved for usage by routers on the network to prevent network outages while improving network reliability, availability and stability.

Route anomaly detection and remediation

Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.

Network traffic routing in distributed computing systems

Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a computing device includes a field programmable gate array ('FPGA') that includes an inbound processing path and outbound processing path in opposite processing directions. The inbound processing path can forward a packet received from the computer network to a buffer on the FPGA instead of the NIC. The outbound processing path includes an outbound multiplexer having a rate limiter circuit that only forwards the received packet from the buffer back to the computer network when a virtual port corresponding to the packet has sufficient transmission allowance. The outbound multiplexer can also periodically increment the transmission allowance based on a target bandwidth for the virtual port.

Network traffic rate limiting in computing systems

Distributed computing systems, devices, and associated methods of remote direct memory access ('RDMA') packet routing are disclosed herein. In one embodiment, a server includes a main processor, a network interface card ('NIC'), and a field programmable gate array (&#x201c;FPGA&#x201d;) operatively coupled to the main processor via the NIC. The FPGA includes an inbound processing path having an inbound packet buffer configured to receive an inbound packet from the computer network, a NIC buffer, and a multiplexer between the inbound packet buffer and the NIC, and between the NIC buffer and the NIC. The FPGA also includes an outbound processing path having an outbound action circuit having an input to receive the outbound packet from the NIC, a first output to the computer network, and a second output to the NIC buffer in the inbound processing path.

Remote direct memory access in computing systems

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Redmond, WA, United States of America

Somesh Chaturmohta