International Business Machines Corporation

Somanath Dash

Charles W Koburger, Iii

Ronald R Troutman

Brian J Machesney

Michael L Kerbaugh

Richard R Garnache

Nitin B Parekh

A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.

Forming wide dielectric-filled isolation trenches in semi-conductors

A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions. An insulating layer is disposed over the first and second portions with thin insulating films formed over the channel regions. The steps of the method include applying a masking layer over the insulating layer having an opening over one of the portions, introducing a first impurity into the channel region of the one portion for channel tailoring purposes, depositing a first conductive refractory material on the thin insulating film located over the channel region of the one portion, removing the masking layer, introducing a second impurity into the channel region of the other portion for channel tailoring purposes and depositing a second conductive material on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material. The first and second conductive materials have different work functions. The first conductive material is, preferably, platinum silicide while the second conductive material may be aluminum.

Method of making dense complementary transistors

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Burlington, VT, United States of America

Somanath Dash