Texas Instruments Corporation

Soman Purushothaman

Keshav Bhaktavatson Chintamani

Steven Craig Bartling

Per Torstein Roine

Sankar Prasad Debnath

Subhankar Das

In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

Enhanced immunity latched logic state retention

The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.

Low area enable flip-flop

This invention is a retention circuit retaining the state of a circuit node driven by a primary drive circuit. This circuit includes cross coupled first and second inverters and a transmission gate. The transmission gate receives a retention mode signal and isolates the retention circuit and the circuit node when a retention mode is active and connects the retention circuit and the circuit node when the retention mode is inactive. In the preferred embodiment the primary drive circuit is constructed of transistors having a standard voltage threshold and the retention circuit is constructed of transistors having a high voltage threshold greater than said standard voltage threshold. A tristate inverter isolates the retention circuit from the circuit node when not in retention mode and supplies an inverse of a signal from output of said first inverter when in retention mode.

High performance low retention mode leakage flip-flop

A single supply level shifter converts an input logic level IN into level shifted OUT and OUT_X. An IN inverter generates level-shifted OUT at an OUT Node. IN is coupled at an INT Node to a Vsupply rail, through an INT_Node PFET that controls the INT Node based on OUT_X. An OUT_X network includes a separate IN_X inverter (generating inverted IN independent of level shifting), and an OUT_X circuit that controls pull-up/down of an OUT_X Node to generate level-shifted OUT_X, receiving control inputs from both IN and IN_X inverters. The OUT_X circuit is a three FET stack: a pull-up/down PFET/NFET pair receives IN_X, and an OUT_X Node control PFET, coupled between the pull-up PFET and the OUT_X Node, receives OUT. Based on OUT and IN_X, the OUT_X circuit generates OUT_X as an inverted OUT (including supplying OUT_X to the INT_Node PFET to control the INT Node (including OUT pull-up).

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Tharuvana, India

Soman Purushothaman