Fujitsu Corporation

Kulicke & Soffa Holdings, Inc.

Other

Solomon I Beilin

Wen-chou Vincent Wang

William T Chou

Michael G Lee

Michael G Peters

James J Roman

Larry Louis Moresco

Yasuhito Takahashi

Mark Thomas McCormack

David Kudzuma

Tetsuzo Yoshimura

David A Horine

Masaaki Inao

Som S Swamy

Thomas Joel Massingill

Yashuhito Takahashi

Lei Zhang

Hunt Hang Jiang

Teruo Murase

Albert Wong Chan

David J Chazan

David G Love

Sundar M Kamath

Connie M Wong

Richard L Wheeler

Jan I Strandberg

David Dung Ngo

Dashun Steve Zhou

Kiyoshi Kuwabara

Long K Truong

Habib Vafi

Lewis T Lipton

Dirk A Zwemer

A method for joining large area semiconductor substrates, a liquid thermoset polymer. Two large area substrates, such as wafers or circuit boards (e.g., rigid or flexible), can be joined together by dispensing a liquid polymer inwardly from the edges of the semiconductor substrates. The substrates can then be pressed together so that the liquid thermoset flows in an outwardly direction ward the edges of the semiconductor substrates. Conducting surfaces on the first and second substrates may contact each other after pressing the liquid thermoset polymer. The liquid thermoset polymer in the formed structure may then be cured to a hardened state. The liquid thermoset polymer preferable has a low viscosity, low levels of ionic contaminants, good adhesion to the substrates, low moisture absorbing properties and favorable thermal expansion properties.

Method for joining large substrates

Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.

Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making

An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.

Single and multilayer waveguides and fabrication process

Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Methods of planarizing structures on wafers and substrates by polishing

A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.

Optical reflective structures and method for making

Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.

Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making

An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide. The method for making an optical apparatus also comprises inserting at least a portion of an optical device within the aperture so that the optical device is positioned to receive light from the first end of the waveguide.

Optical coupling structures and the fabrication processes

A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.

Method of fabricating a substrate with a via connection

Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.

Opto-electronic substrates with electrical and optical interconnections and methods for making

A conductive composition, and articles and methods using the conductive composition are disclosed.

Conductive composition

Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure.

Methods for fabricating flexible circuit structures

Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.

Methods for detaching a layer from a substrate

A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Isolated flip chip of BGA to minimize interconnect stress due to thermal mismatch

Disclosed is an interposer for electrically coupling two electrical components having different coefficients of thermal expansion (CTEs). The interposer has two substrates which have different CTE values, with each substrate having a first surface and a second surface. The interposer has electrical connectors located on the first surfaces of the two substrates, the connectors for making electrical connections to the two corresponding electrical components. A flexible-circuit layer is disposed between the two substrates and interconnects the connectors on the first substrate to the connectors on the second substrate. The two substrates are folded such that their second surfaces confront one another, where they may be attached to one another. General methods of making interposers for electrically coupling two electrical components are disclosed. A first substrate and a sacrificial substrate are encapsulated in an encapsulant material to form a composite substrate, with a second substrate being formed from the cured encapsulate material. Alternatively, the second substrate may be provided by a separate substrate that is encapsulated along with the first substrate and the sacrificial substrate. The surfaces of the composite substrate are polished, and a dielectric layer is formed over a polished surface of the composite substrate. A plurality of electrical traces are formed over the dielectric film. A portion of the composite substrate at its back surface is removed to expose a surface of the sacrificial substrate, and the sacrificial substrate is removed.

Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like

Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.

Growing community of inventors

San Carlos, CA, United States of America

Solomon I Beilin