Samsung Electronics Co., Ltd.

Solji Song

Jeonggi Jin

Jumyong Park

Juil Choi

Jinho Chun

Chungsun Lee

Dongjoon Oh

Hyunsu Hwang

Atsushi Fujisaki

Junyun Kweon

Jinho An

Byeongchan Kim

Taehwa Jeong

Un-Byoung Kang

Ju-Il Choi

Unbyoung Kang

Gyuho Kang

Suhyeon Ku

Provided is a dry etching apparatus including: a plasma process chamber; an edge ring which is arranged in the plasma process chamber and on which a wafer is mounted; a shadow ring positioned to be spaced apart by a first vertical distance above the edge ring during a plasma etching process of the wafer; an operation unit coupled to the shadow ring and having a lift pin that raises and lowers the shadow ring; a fixing portion having a plurality of fixing pins engaged with the lift pin at different positions to fix a lowering point of the shadow ring; and a distance control unit that controls the fixing portion to determine the first vertical distance, wherein the first vertical distance is determined by a first horizontal distance between the wafer and the edge ring.

Dry etching apparatus and wafer etching system using the same

A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.

Semiconductor package and method of manufacturing the same

A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower.

Semiconductor device

A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

Wafer structure and semiconductor device

A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

Semiconductor package

A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

Semiconductor device, semiconductor package and method of manufacturing the same

A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

Semiconductor device having via protective layer

A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

Growing community of inventors

Suwon-si, South Korea

Solji Song