Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Longitude Semiconductor S.a.r.l.

Soichiro Yoshida

Kazuhiko Kajigaya

Yasutoshi Yamada

Tomonori Sekiguchi

Riichiro Takemura

Akira Kotabe

Yoshimitsu Yanagawa

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Semiconductor device having floating body type transistor

A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

Sense amplifier circuit and semiconductor device

A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.

Semiconductor device and data processing system comprising semiconductor device

A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

Semiconductor memory device

A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.

Semiconductor device and semiconductor memory device

A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source and drain which is brought into an electrically floating state. The gate is connected to the signal line, and at least one of the source and drain is connected to a control node that is supplied with a control signal. The control signal is configured to receive a control signal that changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.

A semiconductor device comprises a floating body type transistor and first and second circuits. The transistor has a floating body and a source-drain path inserted between first and second circuit nodes. The first circuit supplies a first signal to the gate of the transistor, and the first signal changes between a first logic level that holds the transistor in a non-conductive state and a second logic level that directs the transistor into a conductive state. The second circuit supplies a first voltage level near the second logic level to the first circuit node and supplies a second voltage level near the second logic level to the second circuit node, each as a level in a state where the transistor is not utilized. Thereby the gate capacitance of the transistor can be kept small as viewed from the gate, and high-speed operation and a reduction in consumption current can be achieved.

A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.

Memory device, semiconductor memory device and control method thereof

A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current, a second bit line selectively connected to the first bit line via the first sense amplifier, a second sense amplifier determining a level of the signal voltage, and a sense amplifier control circuit detecting a temperature of the memory cell array during an operation and controlling an end of an activation period of the first and/or second sense amplifiers in accordance with a detection result of the temperature. In the semiconductor device, the sense amplifier control circuit controls to delay the end of the activation period at least at a predetermined high temperature indicated by the detection result relative to at an ordinary temperature.

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Tokyo, Japan

Soichiro Yoshida