Hitachi, Ltd.

Other

Hitachi Ulsi Engineering Corp.

Soichiro Hashiba

Shuji Ikeda

Toshiaki Yamanaka

Koichiro Ishibashi

Satoshi Meguro

Naotaka Hashimoto

Atsuyoshi Koike

Nobuyuki Moriwaki

Katsuro Sasaki

Isamu Kuramoto

Yutaka Kobayashi

Atsushi Hiraishi

Seigou Yukutake

Shigeru Takahashi

Keiichi Yoshizumi

Kazushi Fukuda

Fumiyuki Kanai

Takashi Hashimoto

Kousuke Okuyama

Yasuko Yoshida

Kazuo Yoshizaki

Kazushi Tomita

Tsuyoshi Tabata

Koichi Imato

Chiemi Hashimoto

Kohji Yamasaki

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Shinji Nishihara

Makoto Saeki

Kiyoshi Nagai

Seiichi Ariga

A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Semiconductor integrated circuit device having capacitance element and

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines. The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

SRAM having load transistor formed above driver transistor

Semiconductor integrated circuit device and process for fabricating the

Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

Process for fabricating a semiconductor integrated circuit device

A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.

Semiconductor integrated circuit device and process of manufacturing the

In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.

Method for manufacturing semiconductor integrated circuit device having

A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.

SRAM with dual word lines overlapping drive transistor gates

Growing community of inventors

Hamuramachi, Japan

Soichiro Hashiba