Hitachi, Ltd.

Hitachi Information Control Systems, Inc.

Hitachi Engineering Ltd

Soichi Takaya

Yoshihiro Miyazaki

Shinichiro Yamaguchi

Tadaaki Bandoh

Koji Matsuda

Jushi Ide

Atsuhiko Nishikawa

Hidekazu Matsumoto

Hiroaki Fukumaru

Masayuki Tanji

Takayuki Morioka

Manabu Araoka

Hirokazu Hirayama

Yukio Kawamoto

Nobuo Akeura

Kenji Hirose

Akira Yamagiwa

Yoshiaki Takahashi

Kenichi Kurosawa

Koji Ozawa

Kenji Kashiwagi

Masao Inoue

Sako Ishikawa

Naoto Miyazaki

Satoru Kayukawa

Masataka Hiramatsu

Hiroshi Oguro

Morioka Takayuki

Kazuhiro Hyuga

A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.

Fault-tolerant computer system

The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

Uninterruptible clock supply apparatus for fault tolerant computer system

A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.

Method of and system for verifying operation concurrence in

A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to access the common memory therein at the time of requesting a read access to a common memory. Other CPUs in the system do not contain common memories, but do include arrangements to access the common memory of the first or second CPU at the time of requesting a read access to a common memory.

Method for controlling multiple common memories and multiple common

Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

System for storing restart address of microprogram, determining the

A co-processor control method intended to speed up data transfer linkage between the co-processor and memory when the co-processor is activated by the main processor, in such a way that the main processor issues an active control signal to the co-processor in the cycle of reading out an operand in the memory onto the data bus by being addressed by the main processor so that the operand on the data bus is directly delivered to the co-processor.

Method for fast establishing a co-processor to memory linkage by main

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Suspended instruction restart processing system based on a checkpoint

A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

Operation control apparatus for a processor having a plurality of

An address translation circuit for translating a logical address into a physical address in a computer system using a virtual storage method includes two high-speed buffers (TLB's) for an instruction and an operand, respectively. One of the buffers is selected for use at the time of a memory access depending on a signal supplied from a processing unit to indicate whether the memory access is related to an instruction cycle or an operant cycle. This configuration enables a high-speed address translation without lowering the TLB hit rate and without increasing the amount of the hardware components.

Address translation circuit including two translation buffers

The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.

Method for restarting execution interrupted due to page fault in a data

Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.

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Hitachi, Japan

Soichi Takaya