Kabushikikaisha Kenwood

Other

Soichi Shinjo

Kenichi Shiraishi

Akihiro Horii

Shoji Matsuda

Tomohiro Saito

Akinori Hashimoto

Hisakazu Katoh

Fumiaki Minematsu

Shigeyuki Itoh

Kazuhiko Shibuya

Yuichi Iwadate

Ryuichi Okazaki

Kenichi Ishihara

A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit , the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

Digital demodulator

A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter ( ), a carrier of the counter ( ) stores outputs from a PN data generator ( ) in a shift register ( ), outputs from a PN comparison circuit ( ) when stored data agree with count values of the counter ( ) are recognized as error pulses, a bit selector ( ) randomly selects, on receiving error pulses and based on outputs from a PN data generator ( ), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit ( ) for outputting to thereby add errors.

Dummy error addition circuit

To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator ( ) supplies address data (A) to a de-interleave memory ( ) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory ( ) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory ( ) only requires space for one superframe.

De-interleave circuit

A BS digital broadcast receiver having no 8PSK-demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder . An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder . Upper four bits of phase error data are searched from a phase error table for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits to by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit A code TCD determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit

BS digital broadcast receiver

A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit ( ), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180&deg;, which are included in a carrier reproduction phase difference detecting circuit ( ), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit ( ) so that the phase obtained from the signal point position coincides with the phase convergence point.

Carrier reproduction circuit

A small scale circuit can be realized. A timing circuit detects a burst symbol signal period from outputs I and Q of a demodulating circuit A for orthogonally detecting a received signal obtained by time-multiplexing digital signals by BPSK, QPSK, and 8PSK modulation. A pattern regeneration circuit outputs the same PN code pattern as on a transmission side. Inverting circuits and output I, Q as RI, RQ for a bit '0' of a PN code pattern, and &minus;I, &minus;Q as RI, RQ for a bit '1'. A phase error table A contains a phase error between the phase of a received signal point as an output of the inverting circuits and and an absolute phase only for a first quadrant of RI, RQ. A phase error detecting processing circuit A reads the phase error data corresponding to the absolute value of RI, RQ, and adjusts the data into the data depending on the current quadrant of the RI, RQ. A carrier regeneration circuit A amends the phase of a reference carrier for use in orthogonal detection such that an adjusted phase error data indicates zero.

Demodulator of receiver

A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter ( ) according to an inversion command signal &ldquo;0&rdquo; or &ldquo;1&rdquo; that is output from an inversion decision circuit ( ) depending on a BPSK signal of a known pattern. A phase error detector ( ) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter ( ). The phase error voltage is passed through a carrier filter ( ), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

A digital broadcasting receiver in which one decoder decodes both Reed-Solomon codes for TMCC and Reed-Solomon codes of an MPEG2-TS packet of a main signal. The received data is divided into a main signal and a TMCC signal. When the separated main signal is subjected to deinterleaving by a deinterleaving circuit ( ), the burst symbol signal is eliminated, and the TMCC signal separated subsequent to the main signal in the last frame of a superframe is added by a selector ( ). The received data to which the TMCC signal is added is decoded by a basic Reed-Solomon code decoder ( ) so as to carry out the error correction of the main signal and the TMCC signal.

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Machida, Japan

Soichi Shinjo