Asahi Kasei Microdevices Corporation

Asahi Kasei Emd Corporation

Sveuciliste U Zagrebu Fakultet Elektrotehnike I Racunarstva

Soichi Morita

Hidenori Mochizuki

Tomislav Suligoj

Marko Koricic

A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBTand a CMOS transistorhybrid-integrated. The HCBThas an open regionopened by etching a device isolating oxide filmsurrounding an n-hill layer. An emitter electrodeA and a collector electrodeB are formed in the open regionand are composed of a polysilicon film having such a thickness as to expose the n-hill layerexposed by etching the device isolating oxide film, and an ultrathin oxide filmcovering at least a part of the n-hill layer. The ultrathin oxide filmfunctions as a protective film for protecting the n-hill layerfrom being etched when the polysilicon film is etched.

Semiconductor device comprising a lateral bipolar transistor

A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBTand a CMOS transistorhybrid-integrated therein. The HCBThas an open regionopened by etching a device isolating oxide filmsurrounding an n-hill layer, an emitter electrodeA and a collector electrodeB each of which is formed in the open regionand is composed of a polysilicon film having such a thickness as to expose the n-hill layerexposed by etching the device isolating oxide film, and an ultrathin oxide filmcovering at least a part of the n-hill layer. The ultrathin oxide filmfunctions as a protective film for protecting the n-hill layerfrom being etched when the polysilicon film is etched to form the emitter electrodeA and the collector electrodeB.

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Tokyo, Japan

Soichi Morita