Nec Corporation

Nippon Kokan Kabushiki Kaisha

Soichi Ito

Yoshihiro Mabuchi

In an automatic positioning/wiring method for a flip-chip semiconductor device which is adapted to design a semiconductor chip including test pads used for inputting/outputting signals in a test, chip terminals respectively arranged on or near the test pads to serve as input/output terminals for an external unit, input/output buffers for exchanging signals with the external unit, and internal circuit blocks which perform predetermined circuit operations in response to signals from the input/output buffers, the internal circuit blocks and the input/output buffers are position/wired in arbitrary regions on the semiconductor chip in an automatic positioning/wiring design process on the basis of a result of a layout position determination process for performing definition such that the input/output buffers and the internal circuit blocks are arranged without discrimination layout regions thereof. A floor plan formation process is performed to arrange the input/output buffers into predetermined groups within the arbitrary region in the form of rows each parallel to one of sides of the semiconductor chip.

Positioning/wiring method for flip-chip semiconductor device

A method of optimizing a power supply network is executed by a CAD system, and estimates current consumptions of component function blocks, then determining routes of power supply lines in such a manner as to pass through areas with local maximum values of the estimated current consumption, determining the entire route of the power supply network, finally regulating width of each power supply line incorporated in the power supply network on the basis of the amount of current passing therethrough so that the power supply network is free from electromigration.

Method of automatically optimizing power supply network for semi-custom

For laying out power supply wiring conductors in integrated circuits, a plurality of function blocks are located, and laid-out positions of power supply wiring conductors of first and second levels are determined on the basis of the located function blocks. Power supply wiring conductors are temporarily laid out by using power supply wiring conductors of third and fourth levels, so as to connect the temporarily laid third and fourth level power supply wiring conductors to the power supply wiring conductors of the first and second levels, so that a power supply network composed of all the power supply wiring conductors is constructed in a desired chip area. Then, a circuit current in the power supply network is calculated, and the current flowing through each power supply wiring conductor is adjusted by conductor width adjustment, deletion or addition of at least one third and/or fourth level power supply wiring conductor, or change of position of an interlayer connection hole between the power supply wiring conductor of the second level and the third and/or fourth level power supply wiring conductor. Thus, optimum power supply wiring conduct layout can be realized without moving the power supply wiring conductors of the first and second levels and therefore without moving the location of the function blocks.

Method for laying out power supply wiring conductors in integrated

A semiconductor integrated circuit of standard-cell type or gate-array type includes a plurality of first cells arranged in a plurality of parallel lines, the first cells having first wirings for supplying power, the first wirings being extended over a plurality of the first cells arranged in the same line in a direction of the same line of the first cells, a second cell disposed in the neighbourhood of some of the first cells and having a dimension larger than the first cells, said second cell having second wirings on a periphery thereof to surround circuit portion of the second cell and means for connecting the second wirings with the first wirings in the first cells in the neighbourhood of the second cell.

Semiconductor integrated circuit having wirings for power supply suited

An apparatus for producing an artificial wave, which comprises: an embankment provided in the sea in parallel to a shore so that the upper portion thereof is exposed above the sea, the embankment having on the off-shore side thereof a slope for causing sea water to crawl up over the embankment in the form of a wave, and on the inshore side thereof a vertical surfaces; a tank, having an open upper end, fitted to the embankment so as to be vertically movable along the vertical surface thereof, the tank having a capacity sufficient to receive sea water having crawled up over the slope of the embankment a plurality of times through the open upper end, a side wall on the inshore side of the tank being capable of being opened and closed; a main buoy, fixed onto a bottom wall of the tank, having buoyancy sufficient to cause substantially the entire of the tank to float up above the sea; and a tank supporting mechanism having a function of supporting the tank at a prescribed position above the sea, the tank supporting mechanism releasing the above-mentioned function thereof when the tank is filled up with sea water and the side wall on the inshore side of the tank being opened; whereby the tank filled up with sea water falls down on the sea along the vertical surface of the embankment and sea water received in the tank is discharged, thereby producing an artificial wave suitable for surfing toward the shore.

Apparatus for producing artificial wave

A semiconductor integrated circuit device comprising a plurality of rows of logic cells, the rows of logic cells being spaced apart from each other to define channel areas therebetween, the logic cells being arranged to form a plurality of function blocks each having a predetermined logic function, and at least one wiring layer overlying the rows of logic cells and the channel areas, the wiring layer comprising a plurality of inter-cell wiring areas extending along the rows of logic cells and including interconnects between desired ones of the logic cells and inter-block wiring areas extending along the channel areas and including interconnects between desired ones of the function blocks. Each of the inter-cell wiring areas comprises wiring sections respectively associated with the function blocks and mostly consisting of wiring sections having widths within a predetermined range.

Semiconductor integrated circuit device

A movable fixed-type semi-submerged construction includes a plurality of legs each having a spat tank attached to its lower end and sunken to rest on the bottom of the sea and a superstructure supported on the legs. A scouring preventing structure including a cylindrical circumferential wall formed with a large number of holes therethrough is arranged at the lower part of each of the legs so as to encircle the spat tank.

Growing community of inventors

Tokyo, Japan

Soichi Ito