Samsung Electronics Co., Ltd.

Korea Institute of Science and Technology

Korea University Research and Business Foundation

Sohyun Park

Yoosang Hwang

Taejin Park

Sunghee Han

Keunnam Kim

Wooyoung Choi

Hyo-Sub Kim

Inkyoung Heo

Eunjung Kim

Junhyeok Ahn

Jin-Hwan Chun

Bong-Soo Kim

Kiseok Lee

Jongmin Kim

Dong-Wan Kim

Eun Ah Kim

Junghoon Han

Hyosub Kim

Chulkwon Park

Yunho Youm

MyungSik Choi

Hui-Jung Kim

Daewon Kim

Seungho Lee

Seung-Heon Lee

Chan-Sic Yoon

Dongoh Kim

Sungmin Park

Myeong-Dong Lee

Jonghyun Kim

Huijung Kim

Sungjun Lim

Hyeran Lee

Hae Jung Son

Chansic Yoon

Youn-seok Choi

Indong Lee

Hakjung Kim

Jiwan Kim

Hyunkyung Kim

Soyoon Park

Hyo Jae Yoon

Jaehwan Cho

Woojin Jeong

Kyoungcho Na

Seryeun Yang

Jong Baek Park

Soyeong Kim

A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Semiconductor device having a cell separation pattern in contact with the bit line contact

A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern

A semiconductor device includes: a stack including a conductive structure and an insulation structure stacked on each other on a substrate, wherein the stack extends in a first direction substantially parallel to an upper surface of the substrate; first, second and third spacers sequentially stacked on each other on a sidewall of the stack in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; and a capping pattern disposed on the second spacer, wherein: the second spacer is an air spacer including air, and an upper surface of a portion of the third spacer is substantially coplanar with an upper surface of the capping pattern.

Semiconductor devices having air spacer

Provided is a semiconductor device including a substrate including a cell array area and a peripheral circuit area and including a plurality of first active areas defined in the cell array area and at least one second active area defined in the peripheral circuit area; a plurality of bit lines arranged in the cell array area of the substrate and extending in a first direction; a plurality of cell pad structures arranged between the bit lines and each including a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of the first active area; and a peripheral circuit gate electrode disposed on the peripheral circuit area of the substrate and including a second conductive layer, a second intermediate layer, and a second metal layer sequentially arranged on the at least one second active area.

Semiconductor device and methods of manufacturing the same

A semiconductor device includes a one-time programmable (OTP) memory device, a key register and a key protection control logic. The OTP memory device stores a secret value, a key protection bit indicating whether to protect the secret value, and an end of life bit indicating whether to discard the semiconductor device. The key register loads the secret value from the OTP memory device and stores the secret value. The key protection control logic controls loading of the secret value from the OTP memory device to the key register based on the key protection bit and the end of life bit. Security of the secret value is enhanced and utilization of the secret value is optimized using the key protection bit and the end of life bit.

Semiconductor device and method of operating the same

Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

Semiconductor devices

A computing device in a trusted computing (TC) system and an attestation method thereof are provided. The computing device includes at least one processor configured to operate as instructed by program code, the program code including: transmission code configured to cause the at least one processor to transmit, to a master controller, a first identification (ID) for a first device selected among a plurality of devices included in the TC system, a second ID for a second device selected among the plurality of devices, and a nonce; and attestation code configured to cause the at least one processor to perform attestation for the first device and the second device based on an aggregated signature, wherein the aggregated signature is based on generation of a first signature, by the first device, by using the nonce, and generation of a second signature, by the second device, by using the first signature.

Computing device in a trusted computing system and attestation method thereof

The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Semiconductor devices having improved electrical characteristics and methods of fabricating the same

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Semiconductor memory device having spacer capping pattern disposed between burried dielectic pattern and an air gap and method of fabricating same

A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

Semiconductor memory device and method of fabricating the same

The present invention relates to a thermoelectric measurement system based on a liquid eutectic gallium-indium electrode, whereby thermoelectric performance can be measured with excellent efficiency and high reproducibility even without construction of expensive equipment, various organic molecules as well as large-area molecular layers can be measured, and various thermoelectric materials, such as inorganic materials and inorganic-organic composite materials, can be measured. In addition, non-toxic liquid metal EGaIn is used as an upper electrode, so the damage to even a substance of measurement in the form of a nano-level thin film can be minimized, and the measurement of thermoelectric performance can be performed on even nano- to micro-level organic thermoelectric elements. Therefore, the thermoelectric measurement system is widely utilized across the thermoelectric element industry.

Thermoelectric measurement system and thermoelectric device based on liquid eutectic gallium-indium electrode

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Semiconductor memory device and method of fabricating same

A conjugated polymer that is an electron donor, that is soluble without aggregation, that is solution-coatable and is dryable at a temperature below 70&#xb0; C., that has an energy conversion efficiency of 7 % or more over an area of 5 cmor more, and that is composed of a repeating unit represented by Chemical Formula 1A below:  where x is a real number from 0.1 to 0.2; and n is an integer from 1 to 1,000. The conjugated polymer forms a uniform thin film over a large area of, for example, an organic solar cell, without a heat treatment due to superior solubility and crystallinity at low temperature and, thus, allows fabrication of an organic solar cell with high efficiency at a low temperature.

Conjugated polymer for a photoactive layer, a coating composition including the conjugated polymer, and an organic solar cell including the photoactive layer

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Seoul, South Korea

Sohyun Park