Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Sohei Kushida

Satoshi Kamiya

Tatsuya Tokue

Haruya Iwata

Takayuki Mori

Takashi Takemoto

A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.

Control method and semiconductor integrated circuit

According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.

According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

Semiconductor device

A decoding device has a buffer configured in memory to store N code streams and N decoders connected in series. Each of N decoders decodes a corresponding code steam and sequentially generates partial symbols of M bit width each unit cycle. Among the N decoders, i (i&#x3e;=2) stage decoders stores multiple probabilistic models in the memory. In each unit cycle, the decoder receives an input of i&#x2212;1 partial symbols which contains partial symbols generated by the i&#x2212;1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i&#x2212;1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with previously entered i&#x2212;1 partial symbols.

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Tokyo, Japan

Sohei Kushida