Nxp B.v.

Soenke Ostertun

Vitaly Ocheretny

Franz Amtmann

Björn Fay

Bjorn Fay

Michael Ziesmann

Martin Feldhofer

Maurits Storms

Alexandre Frey

Christoph Hans Joachim Garbe

Frantisek Cevela

Joachim Christoph Hans Garbe

Alicia Da Conceicao

Andrea Castelnuovo

A non-volatile memory (NVM) system includes a memory array divided into physical pages, control circuitry, and a global transaction log (GTL). Each physical page is configured to store a corresponding payload and corresponding metadata for the physical page. Each entry of the GTL is configured to store a transaction descriptor identifying a transaction and a corresponding physical page used by the transaction. Each entry also has a corresponding transaction log entry (TLE) flag. The control circuitry is configured to populate the entries of the GTL in sequential order with each new transaction, and, in response to completing storing the transaction descriptor for a new transaction, program the corresponding TLE flag by toggling its logic state.

Power tearing protection within a non-volatile memory (NVM)

In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.

Non-volatile memory system with secure detection of virgin memory cells

Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.

Method to increase the usable word width of a memory providing an error correction scheme

A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.

Non-volative memory system configured to mitigate errors in read and write operations

In accordance with a first aspect of the present disclosure, a non-volatile memory is provided, comprising: a plurality of storage elements; a plurality of access transistors, said access transistors being connected to one or more of said storage elements; a measurement unit, wherein said measurement unit is configured to measure a variation between electrical characteristics of said access transistors; a processing unit configured to use said variation between electric characteristics as a physical unclonable function. In accordance with a second aspect of the present disclosure, a corresponding method of manufacturing a non-volatile memory is conceived.

Non-volatile memory with physical unclonable function

There is described a driver circuit () for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch () comprising a first latch input terminal (), a first latch control terminal (), a latch voltage supply terminal (), a first latch output terminal (), and a second latch output terminal (), wherein the level shifter latch () is adapted to provide, in dependency of a voltage at the first latch input terminal (), one of a first voltage and a second voltage at the first latch output terminal () and the other one of the first voltage and the second voltage at the second latch output terminal (), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal () and the second voltage is dependent on a voltage applied to the first latch control terminal (), (b) a first output stage () comprising a first switching element (N, N), a second switching element (N), a first voltage supply terminal (), a second voltage supply terminal (), and a first biasing voltage output terminal (), wherein the first switching element (N, N) is adapted to connect the first biasing voltage output terminal () to the first voltage supply terminal () in dependency of the voltage at the first latch output terminal (), and wherein the second switching element (N) is adapted to connect the first biasing voltage output terminal () to the second voltage supply terminal () in dependency of the voltage at the second latch output terminal (), and (c) a second output stage () comprising a third switching element (N), a fourth switching element (N), a third voltage supply terminal (), a fourth voltage supply terminal (), and a second biasing voltage output terminal (), wherein the third switching element (N) is adapted to connect the second biasing voltage output terminal () to the third voltage supply terminal () in dependency of the voltage at the first latch output terminal (), and wherein the fourth switching element (N) is adapted to connect the second biasing voltage output terminal () to the fourth voltage supply terminal () in dependency of the voltage at the second latch output terminal ().There is also described a memory system and a method of operating the driver circuit.

Driver circuit for memory devices

According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.

Tamper resistant IC

There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit. The first input terminal is adapted to receive a first signal being indicative for a signal at a first stage of a driver of the semiconductor device, the driver being capable to drive signals internally to the semiconductor device. The second input terminal is adapted to receive a second signal being indicative for a signal at a second stage of the driver of the semiconductor device. The comparison unit is adapted to compare the first signal and the second signal and to determine a time period during which the signals are equal, wherein the determined time period is indicative for a potential attack, if the determined time period is above a predefined threshold.

Detection arrangement

An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a 'programmed state', the zero state as an 'erased state'. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

Electronic counter in non-volatile limited endurance memory

A method of controlling a pre-charge process of a data line () in an integrated circuit () comprises the step of monitoring a rate of change of a voltage applied to the data line () for enhancing the security. Further a respective integrated circuit () is disclosed.

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Wedel, Germany

Soenke Ostertun