Deutsche Itt Industries Gmbh

Intermetall, Division of Ditti

Soenke Mehrgardt

Peter M Flamm

Ljubomir Micic

Bernhard Ehret

Ulrich Theus

Lothar Blossfeld

Martin Winterer

Heinrich Pfeifer

Hans-Juergen Desor

Thomas Fischer

Rainer Schweer

Heinrich Schemmann

Hans-Jurgen Desor

A bus arbitration method for a multimaster system comprising a plurality of masters sharing a global data bus and a plurality of bus arbiters sharing a global identification bus. Each active bus arbiter applies to the identification bus a bus request signal containing a k-bit-wide identification word representative of the priority of the master associated with the bus arbiter. In each prioritization step of the bus grant cycle, a logic level is produced on the identification bus by logically combining bits of equal significance. This logic level is then compared with the corresponding bits of the applied identification words. The k bits of the identification words of the bus arbiters are placed on the identification bus on a time-graded basis; in each prioritization step of the bus grant cycle, only those bits of the identification words are placed on the identification bus which are of equal significance, and in each prioritization step of the bus grant cycle, those bus arbiters whose identification word bit in the prioritization step does not match the logic level of the identification bus are eliminated from the bus arbitration of the bus gram cycle.

Apparatus and methods for bus arbitration in a multimaster system

For improved offset compensation, a Hall sensor is provided with a device for orthogonally switching the Hall detector supply current and the Hall-voltage taps. A summing device determines an offset-compensated Hall-voltage value from first and second predetermined Hall-voltage values. The Hall-voltage values are formed by means of a Hall detector containing at least first and second Hall cells for offset-voltage precompensation. The first and second Hall cells are identical and are orthogonally switchable. The geometrical orientation of the first and second Hall cells includes an angle other than 0.degree. and 180.degree..

Offset-compensated hall sensor having plural hall detectors having

A digital television-signal-processing circuit for a composite color signal is sampled with a first clock signal. The digitized composite color signal is reconverted with a line-locked second clock signal. The two clock signals have the same frequency. A second phase-locked loop for controlling the phase of the horizontal pulse includes a locked oscillator and is loosely coupled to a first phase-locked loop which generates a horizontal reference clock. The decoupling of the data, which is referred to the two clock signals, takes place in a dual-port read/write memory which is written into synchronously with the first clock signal and read from synchronously with the second clock signal.

Digital television-signal-processing circuit with orthogonal output clock

In a median filter, signals received at the input are fed to a cascade of delay elements whose number is equal to the degree N of the median filter. The signals at the outputs of the delay elements which preceded the signal received at the input are fed to N subtracters which form the differences between the signal at the input and the N preceding signals. The signs of the differences are stored in shift registers, and upon receipt of a new signal at the input, they are shifted by one place. From the signs of the differences, the selection unit determines the median as the signal for which N/2 differences have negative signs and N/2 differences have positive signs.

Median filter

A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed. The use of delayed branching is supplemented by the skip technique. The central processor does not utilize interrupt control. Rather, a scheduler selectively changes the sequence in which a program operates in response to an external or internal task request only at the end of the segment currently being executed so that the current program segment is concluded without interruption.

Harvard architecture microprocessor with arithmetic operations and

A digital color-signal-processing circuit generates a phase-angle signal and a magnitude signal as outputs in response to an R-Y color-difference signal and a B-Y color-difference signal. The circuit includes a resolver which convertes cartesian coordinate representations of the color-difference signals into polar coordinate representations of the phase-angle signal and the magnitude signal. The phase-angle signal carries the hue information, which is processed in a hue stage. The magnitude signal carries the saturation information, which is processed in a saturation stage. The processed phase-angle signal and the processed magnitude signal are reconverted to cartesian coordinate representations of the R-Y and B-Y color-difference signals in a reconverting resolver.

Digital color-signal-processing circuit that provides independent

A deflection processor generates deflection signals such that the video information of the received signal is visible on the picture tube screen during all movements of the cathode ray beam. The video signal, after being digitized by means of a clock signal, is written into a random-access memory and is read therefrom in such a way that the individual pixels occupy the correct positions on the screen. This is done under control of a memory controller. The digital signals of the memory are applied to a tube-error-compensating stage and to the picture tube via digital-to-analog converters. This arrangement eliminates the rigid dependence on sawtooth deflection signals and permits the waveforms of the deflection signals to be freely selected according to requirements.

Digital circuit system for television receivers with cathode ray picture

The signal path of a nonrecursive digital filter contains a series combination of like delay elements each providing a delay equal to the period of a clock signal or to a multiple thereof, each of the delay elements having a subtracter and a read-only memory associated therewith. The minuend inputs of each of the subtracters associated with the first half of delay elements is connected to the input of the associated delay element, and that of each of the substracters associated with the second half of delay elements to the output of the associated delay element, while the subtrahend inputs of all subtracters are connected to the center tap of the series combination of delay elements and to the first input of an adder. The output of each of the subtracters is coupled to the address input of the associated read-only memory, which has its output connected to one of the inputs of a multiple-input adder. The output of the latter is fed to the second input of the adder. Each read-only memory contains the function e=bd, where d is the output signal of the subtracter, and b is a value dependent on the difference between the center-tap signal value and the input-signal value of the respective delay element of the first half of delay elements or the output-signal value of the respective delay element of the second half. This digital filter shows adaptive behavior.

Nonrecursive digital filter

This circuit simultaneously provides the sine- and cosine-function values for one and the same digital argument from any of the quadrants of the sine and cosine functions. Stored in the two halves of a read-only memory are the unsigned function values of the first half-quadrant of the cosine function in the direction of increasing arguments and of the second half-quadrant in the direction of decreasing arguments, respectively. The number of bits of the argument is greater than the number of bits of the function values, including the sign bit, by two. By skillful inversion of the addresses and the read-out function values using multiple-inverter blocks in conjunction with multiple-switch units sine- and cosine-function values can be generated for all four quadrants both in the one's and in the two's complement code. If the argument is formed by an accumulator fed with the frequency determining digital word, the digital circuit is a digital sine-/cosine-wave oscillator.

Digital circuit for simultaneously generating digital sine- and

Instead of fine-controlling the horizontal deflection signal in a digital television receiver by means of two phase-locked loops and gate-delay stages as is done in prior art arrangements, in the horizontal-deflection circuit according to the invention, a first digital word delivered by a first phase-locked loop and representative of the horizontal frequency is added in an adder to a suitably amplified third digital word delivered by a phase comparator of a second phase-locked loop. The output of the adder is fed to the control input of a digital sine-wave generator which drives a frequency divider. The latter delivers the horizontal deflection signal, which drives the horizontal output stage. The phase comparator is fed with the horizontal flyback signal, which is derived from the horizontal deflection signal, and a second digital word generated by the first phase-locked loop and representative of the desired phase position of the flyback signal.

Digital horizontal-deflection circuit

This control circuit adjusts two signal waveforms to a phase difference of exactly 90.degree. and to exactly equal amplitudes of the respective frequency components. It is a digital circuit containing a phase control stage (pr) and an amplitude control stage (ar). The control circuit (r) delivers first and second quadrature signals (q1, q2) which are multiplied together to obtain a phase control value (p) which is multiplied by one of the digitized quadrature analog signals and added vectorially to the second digital signal. The two signals thus brought to a phase difference of exactly 90.degree. are the two phase-corrected digital signals (p1, p2). In the amplitude control stage (ar), one of the two phase-corrected digital signals (p2, p1) is multiplied by the amplitude control value (g) from the amplitude comparator (av1, av2), and the product is the amplitude- and phase-corrected quadrature signal (q2, q1) belonging to the other quadrature signal (q1, q2).

Circuit for controlling two signals approximately 90 degree apart in

A monolithic integrated digital-to-analog converter makes use of rotating current-source control (dynamic element matching). After the conversion of a digital input signal into a code containing a sequence of first binary conditions corresponding to the numerical value of the input signal (so-called thermometer code), the bit switches of possibly same-sized current sources are rotatingly controlled in the sense of being selected, so that it becomes possible in the manufacture of the monolithic integrated digital-to-analog converters to balance out the manufacturing tolerances or process variations of the current sources.

Monolithic integrated digital-to-analog converter

A digital delay arrangement generates a delay time which is a noninteger multiple of the period of a system clock frequency. The arrangement includes a digital delay circuit having a delay time equal to the period, a multiplier for the part of the noninteger multiplier, b, being less than one, a further multiplier for 1- b, an adder and a peaking filter clocked by the system clock.

Delay circuit for digital signals

To raise the integration level of a video recorder, and to provide a uniform circuit concept suitable for all three color-television standard (PAL, NTSC, SECAM) which, in particular, requires only slight modifications for adaptation to the respective standard, signal processing is performed by fast digital circuits whose signals are stored on the recording medium not in digital form, but after digital-to-analog conversion. The composite color signal is converted into digital form by a fast analog-to-digital converter (aw) whose sampling signal (fc) has a fixed frequency (Fc) for all three color-television standards. Digital signal processing in the chroma channel is performed at a fixed subcarrier frequency (zt) for all three color-television standards which is an integral subharmonic of the sampling frequency (Fc).

Video recorder with a magnetic recording medium in the form of a tape

The frequency of a signal is classified in at least two nonoverlapping frequency ranges using the variable frequency of a clock signal as a reference. The clock signal is applied to the count input of a first up counter, and the signal to the reset input of this up counter and to the enable input of a first buffer. The parallel inputs of the first buffer are connected to the count outputs of the up counter, and the parallel outputs of this buffer are coupled to the parallel inputs of a multiple comparator in which each nonoverlapping frequency range is assigned a digital output. Each of these digital outputs is connected to the D input of a D flip-flop, which is clocked by the signal, and to one of the two inputs of an EXOR gate having its other input connected to the Q output of the associated flip-flop. The signal is also fed to the count input of a second up counter whose reset input is connected to the output of an OR gate having each of its inputs connected to the output of one of the EXOR gates, and the count outputs of the second up counter are each coupled to one of the inputs of an AND gate. The output of the latter is connected to the enable input of a second buffer whose inputs are each connected to the Q output of one of the D flip-flops and whose outputs are the frequency-range outputs.

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March, Germany

Soenke Mehrgardt