Taiwan Semiconductor Manufacturing Comp. Ltd.

So Wein Kuo

Tsu Shih

Chung-Te Lin

Chung-Long Chang

Chia Shiung Tsai

Chu-Wei Hu

Shing-Long Lee

Jiue-Wen Weng

A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Self aligned channel implant, elevated S/D process by gate electrode damascene

An apparatus and method for the hot bake to remove moisture from photoresist that has been deposited on semiconductor wafers prior to a dry plasma etch process. A wafer carrier containing semiconductor wafers on which a photoresist has been deposited is placed in a load lock chamber having a source of heat such as a heating plate or a high intensity light source. The source of the heat is activated and the semiconductor wafers are brought to a temperature sufficiently high and of a sufficient duration as to eliminate any moisture present in the photoresist mask. The load lock chamber is evacuated to eliminate any moisture or contaminants, filled with nitrogen to eliminate any residual of moisture or contaminants, and then evacuated to prepare the chamber to exposed to the atmosphere present in a dry plasma etch chamber. An exit lock of the load lock chamber is opened and the wafer carrier is placed in the dry plasma etch chamber for the execution of the dry plasma etch process.

In situ photoresist hot bake in loading chamber of dry etch

A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas. Finally, there is stripped through an oxygen containing plasma stripping method the patterned photoresist layer and the fluoropolymer residue layer from the patterned fluorine containing plasma etched layer. The oxygen containing plasma stripping method employs a second etchant gas composition comprising a fluorine containing etchant gas and an oxygen containing etchant gas.

Plasma etch method for forming residue free fluorine containing plasma

An improved method of plasma-activated reactive subtractive etching of polycide layers by mixtures of sulfur hexafluoride, hydrogen bromide, and oxygen gases is achieved. After the subtractive etching of the polycide layer is performed, a purging operation of the reaction chamber by admission of a non-reactive gas such as nitrogen followed by evacuation results in the removal of water vapor and other residual species. This purging step inhibits the formation of needle-like crystals of residual compounds thought to form by chemical reaction between hydrogen bromide and water vapor and other species. Such needle-like crystalline residues can be construed as defects in the etched polycide patterns, and their minimization results in increased manufacturing yields after visual inspection. Additionally, the reduced incidence of residual crystalline residues is beneficial in helping to improve subsequent integrated circuit reliability.

Method for reduction of polycide residues

Using an APM solution to clean both the front and backside of a semiconductor wafer significantly reduces the residue from chemical mechanical polishing. A low residue count holds the wafer more securely to the electrostatic chuck, thus improving processing, reducing wear on the electrostatic chuck, and increasing its lifetime.

Method for CMP cleaning improvement

A method to produce a contact or via opening and filled metallurgy for CMOS or other integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer structure is formed thereover comprising a first layer of tetraethoxysilane (TEOS), a second layer of borophospho-TEOS (BPTEOS), and a third layer of TEOS. A contact opening is etched through the insulating layer structure not covered by a mask to the semiconductor device structures to be electrically contacted wherein the profile of the contact opening is not vertical because the BPTEOS layer is etched. horizontally more than the first and third TEOS layers and wherein native oxide builds up on the sidewalls of the contact opening. The substrate is dipped into a hydrofluoric acid solution to remove the native oxide on the sidewalls of the contact opening whereby the hydrofluoric acid etches the BPTEOS layer at a slower rate than it etches the first and third TEOS layers whereby the contact profile is made vertical. A glue layer is sputter deposited over the surface of the insulating layer structure and within the contact opening. A conducting layer is deposited over the glue layer filling the contact opening completing the electrical contact in the fabrication of the integrated circuit device.

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Hsin-Chu, Taiwan

So Wein Kuo