Sumitomo Electric Industries, Limited

Renesas Electronics Corporation

International Business Machines Corporation

Honda Motor Co., Ltd.

Cornell Research Foundation Inc.

So Tanaka

Michitomo Iiyama

Ryosuke Kubota

Shunsuke Yamada

Hiroshi Inada

Taku Horii

Takao Nakamura

Shinji Kimura

Kyoko Okita

Masayuki Kobayashi

Daisuke Hamajima

Takeyoshi Masuda

Hirotaka Oomori

Takayuki Nishiura

Toru Hiyoshi

Hideaki Takada

Takashi Iwasaki

Taro Nishiguchi

Hiroki Tawa

Rudolf M Tromp

Hideto Tamaso

Tatsuya Kuroda

Akihiro Moto

Kazuyoshi Sato

Mitsuhiko Sakai

Tatsuya Tanabe

Jiro Shinkai

Nobuyuki Ikoma

Kenichi Sawada

Ren Kimura

Kenji Kanbara

Akira Matsushima

Takahiro Matsui

Masaki Kijima

Yoshisumi Kawabata

Tatsushi Kaneda

Yusuke Horie

Takatoshi Okamoto

Christopher C Umbach

Jack M Blakely

Maki Hamada

Kazuhito Kobashi

A semiconductor module includes: a circuit board; a semiconductor chip having a first electrode pad on a first surface, bonded to the circuit board at a second surface that is opposite to the first surface, and having side surfaces intersecting the first surface and the second surface; an external terminal electrically connected to the first electrode pad; and an insulating member configured to fix the external terminal, wherein by the insulating member contacting the side surfaces of the semiconductor chip at a plurality of locations, parallel movement and rotational movement of the semiconductor chip relative to the insulating member in a plane parallel, to the first surface are restricted, and wherein the external terminal penetrates the insulating member.

Semiconductor module

A semiconductor device includes: a base plate having a first surface and having a first contact area in the first surface; a metal plate having a second surface, disposed such that the second surface faces the first surface, and having a second contact area in the second surface; a bonding material disposed between the first surface and the second surface and in contact with the first contact area and the second contact area to bond the metal plate and the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate; a semiconductor element mounted to the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space above the base plate, wherein outside the second contact area, the second surface has a non-contact area that is not in contact with the bonding material, wherein on the base plate, a groove portion facing the non-contact area and surrounding the first contact area is provided, and wherein, in a plan view as viewed in a thickness direction of the base plate, an inner periphery of a corner portion of the groove portion has a first curve.

Semiconductor device

The silicon carbide semiconductor chip includes a silicon carbide substrate, a first insulating film on the silicon carbide substrate, and a second insulating film on the first insulating film. The silicon carbide substrate has a first main surface in contact with the first insulating film, a second main surface, and an outer peripheral surface. The resin covers both of the outer peripheral surface and the second insulating film. The second insulating film has a Young's modulus lower than that of the resin. The second insulating film has a thermal expansion coefficient higher than that of the silicon carbide substrate and higher than that of the resin. The second insulating film includes a first outer peripheral end portion. In a cross section perpendicular to the first main surface, the first outer peripheral end portion is provided along the outer peripheral surface.

Silicon carbide semiconductor device including a resin covering a silicon carbide semiconductor chip

A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1&#xd7;10cm, and is not more than 1&#xd7;10cm.

Silicon carbide semiconductor device

A method for manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide layer including an n-type region having an n conductivity type and a p-type region having a p conductivity type, forming a material layer containing titanium, aluminum, and silicon on the n-type region and the p-type region, and forming an electrode layer in contact with the n-type region and the p-type region by heating the material layer. In forming a material layer, composition of the material layer is determined such that a point (x, y, z) (x, y, and z each being a numeric value greater than 0) representing a composition ratio among titanium, aluminum, and silicon is included in a first triangular pyramidal region having four points of the origin (0, 0, 0), a point (1, 2, 2), a point (2, 1, 2) and a point (2, 2, 1) as vertices.

Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of &#x2212;5 V is applied to the gate electrode for 100 hours at a temperature of 175&#xb0; C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.

Silicon carbide semiconductor device and method for manufacturing the same

The gate electrode is provided on the gate insulating film. The interlayer insulating film is provided to cover the gate electrode. The interlayer insulating film includes a first insulating film which is in contact with the gate electrode, contains silicon atoms, and contains neither phosphorus atoms nor boron atoms, a second insulating film which is provided on the first insulating film and contains silicon atoms and at least one of phosphorus atoms and boron atoms, and a third insulating film which contains silicon atoms and contains neither phosphorus atoms nor boron atoms. The second insulating film has a first surface which is in contact with the first insulating film, a second surface opposite to the first surface, and a third surface which connects the first surface and the second surface. The third insulating film is in contact with at least one of the second surface and the third surface.

Silicon carbide semiconductor device having gate electrode

A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 &#x3bc;m. A dislocation density is not more than 500/mmat an arbitrary region having an area of 1 mmin a region within 5 mm from an outer circumferential end portion of the first main surface toward a center of the first main surface. Accordingly, there is provided a silicon carbide semiconductor substrate allowing for suppression of generation of cracks.

Silicon carbide semiconductor substrate and method for manufacturing same

A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes a step of preparing a SiC substrate, a step of fixing the SiC substrate on an electrostatic chuck and heat-treating the SiC substrate, and a step of performing ion implantation treatment on the SiC substrate fixed on the electrostatic chuck and heat-treated. The step of heat-treating includes an outer circumferential-side chucking step which generates an electrostatic attraction force between an outer circumferential region of the SiC substrate and an outer circumferential portion of the electrostatic chuck, the outer circumferential portion facing the outer circumferential region, and an inner circumferential-side chucking step which is started after the outer circumferential-side chucking step is started, and generates an electrostatic attraction force between an inner circumferential region of the SiC substrate and an inner circumferential portion of the electrostatic chuck, the inner circumferential portion facing the inner circumferential region.

Method for manufacturing semiconductor device including a heat treatment step

A method for manufacturing a silicon carbide substrate includes the following steps. There is prepared a silicon carbide single crystal substrate having a first main surface, a second main surface, and a first side end portion, the second main surface being opposite to the first main surface, the first side end portion connecting the first main surface and the second main surface to each other, the first main surface having a width with a maximum value of more than 100 mm. A silicon carbide epitaxial layer is formed in contact with the first side end portion, the first main surface, and a boundary between the first main surface and the first side end portion. The silicon carbide epitaxial layer formed in contact with the first side end portion and the boundary is removed.

Silicon carbide substrate, silicon carbide semiconductor device, and methods for manufacturing silicon carbide substrate and silicon carbide semiconductor device

A first impurity region is formed by ion implantation of a first impurity into a first main surface of a silicon carbide substrate. A metal layer is formed in contact with the first impurity region. By annealing the silicon carbide substrate and the metal layer, an electrode is formed. The metal layer is formed such that a concentration of a first impurity at a boundary portion between the metal layer and the first impurity region becomes less than a maximum value of a concentration of the first impurity in the first impurity region. The electrode is formed such that a concentration of the first impurity at a boundary portion between the electrode and the first impurity region becomes not less than 80% of a maximum value of a concentration of the first impurity in the first impurity region in a normal direction.

Silicon carbide semiconductor device and method of manufacturing same

Exhaust passage system in an outboard engine unit includes: an engine-side exhaust pipe; a downstream exhaust pipe for directing exhaust gas downstream from the engine-side exhaust pipe, a lower end portion of the engine-side exhaust pipe and an upper end portion of the downstream exhaust pipe being positioned in horizontally parallel to each other and horizontally overlap each other so as to provide fluid communication therebetween via a through-hole formed in the overlapping portions of the end portions; and a vertical partition wall provided, in an upper end region of the overlapping portions for hampering back-flows of fluid.

Outboard engine unit

There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 &#x3bc;m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.

Inspection method of compound semiconductor substrate, compound semiconductor substrate, surface treatment method of compound semiconductor substrate, and method of producing compound semiconductor crystal

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Osaka, Japan

So Tanaka