Digital Equipment Corporation

Snehamay Kundu

Donald F Hooper

David B Fite, Jr

James L Finnerty

David F Wall

Edward G Fortmiller

Donald F Hopper

In the synthesis procedure for circuit design, a convenient notation is used for the insertion of new instances in the consequence portion of a rule having a antecedent form and a consequence portion. The notation is of the form

Rule structure for insertion of new elements in a circuit design

In a procedure for synthesizing circuit designs, a SYNTHESIZE command in a consequence portion of a rule can be used to control the creation of bit-level instances from a description of a more abstract instance whose interface consists of multi-bit signals. The `synthesize` command has a form that identifies multibit signal/part objects in the data base relative to the current multi-bit instance, which are then synthesized over the range of most-significant to least significant bit. A collection of rules, called macrorules are enclosed within a `synthesize` command. An iteration controlled by 'current bit', ranging from least significant to most significant bit, ensues. At each step of the iteration, all macrorules are tested and applied if they are `true`. The macrorules can query whether the current bit is a function of the least or most significant bits. The macrorules can also establish connectivity to any signal bit relative to the current, the least significant or the most significant bit. Signals which represent numeric constants, are converted to the correct binary value for each bit of the bitwise synthesis. During this process, new signal names with bit subscripts are generated, if needed, and connections are made so that the resulting data base represents an electrically connected circuit.

Bitwise implementation mechanism for a circuit design synthesis procedure

A procedure is described for the synthesis and transformation of a logic circuit design, provided by the designers, into a database capable of being used to fabricate the actual circuit. The procedure involves the use of model instances which represent the use of circuit components. The original model instances can be associated with groups of rules that determine resulting configurations of generally different model instances or groups of model instances. The rules are tested and, in the presence of a `true` result, a new model instance (or model instances) can replace one or more original model instances in the data base. The rules associated with a model type (or definition) are rules derived by a design model engineer and can include coupled model instances. The rules can be associated with model definitions, as well as model instances. The data structures associated with each model instance indicate the model interface as well as the model interface port and permit a path to followed in the circuit in either the forward or the reverse signal direction. The model instances reside within model definitions which reside with design data in hierarchical form. The rules controlling the synthesis and transformation of the circuit are contained in a separate hierarchy of data structures or knowledge structures to which reference can be made by design data structures.

Procedure and data structure for synthesis and transformation of logic

In a procedure for the synthesis of logic circuits in which the components of the logic circuits are replaced by model instances related to data files stored in the procedure data base, a rule structure is described that permits the synthesis of the logic circuit by testing the model instances through a process included in a first or antecedent portion of the rule, and in the event that the conditions of the rule are fulfilled, then the consequence portion of the rule is executed. The consequence portion of the rule can include the replacement of one or more model instances of the logic circuit with one or more different model instances while retaining the functional or logical equivalence between the instances before and after the application of the rule. The rule includes a field that permits automatic prioritization a plurality of rules. The rules are written in a format that is similar to normal grammatical construction and, therefore, easily learned.

Rule structure in a procedure for synthesis of logic circuits

A method for simplifying Boolean AND-OR logic in a circuit synthesis system. Rules are associated with model instances representing circuit components and contained in a data base. During testing of an antecedent portion of a rule, a benefit value representing a decrease in pins or an improvement in timing is calculated and compared to the value of a 'benefit variable', which represents a minimum acceptable benefit that must be gained from application of a rule. If a sufficient benefit will result from application of the rule, the rule is applied. Some rules simplify the circuit and then recursively call themselves. Some rules indicate other model instances in the data base, search the set of rules for rules applicable to that model instance, and apply the rule discovered during the search.

Method of minimizing sum-of-product cases in a heterogeneous data base

A logic method for accessing rules in a logic circuit synthesis system. Application of rules in a data base results in replacement of one or more model instances with other model instances or in alteration of values associated with the model instances or in the alteration of parameter values in the data base. Model instances are designated as VISIBLE or INVISIBLE, INVISIBLE model instances are ignored during logic circuit synthesis. VISIBLE model instances may be NEW or INACTIVE. All VISIBLE model instances are initially NEW. If no rule assciated with a model instance is TRUE, the model instance becomes INACTIVE. If at least one rule associated with a model instance is TRUE, one or more model instances are replaced and all inserted model instances and model instances directly connected to the inserted model instances become NEW. The number of model instances a rule will replace is called a SIZEWIN value of the rule. During synthesis, each VISIBLE, NEW model instance is paired with its associated rule having the greatest SIZEWIN value. The instance-rule pairs are grouped by SIZEWIN value and the rules of the groups having the greatest SIZEWIN value are tested first. If a model instance has been replaced by a previously executed rule, it is designated as DELETED and its associated, paired rule evaluates to FALSE.

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Marlboro, MA, United States of America

Snehamay Kundu