Nxp Usa, Inc.

Sneha Mishra

Sourav Roy

Arvind Kaushik

Joseph Gergen

Howard Dewey Owens

In a hardware-accelerated computing systems, calls are made from a processor to an accelerator core. The hardware-accelerated computing system includes a processor core having a stack, an accelerator, and an accelerator scheduler. The computing system is configured to process an accelerator command by the processor core issuing an accelerator command to the accelerator scheduler during execution of a task the accelerator scheduler receiving the accelerator command and requesting data from the stack, the processor sending the requested data from the stack to the accelerator scheduler, the accelerator scheduler sending the requested data to the accelerator and sending a write response to the processor, the accelerator processing the accelerator command, and the processor continuing execution of the task. The processor pauses execution of the task upon issuing the accelerator command and resumes execution of the task upon receiving the write response from the accelerator scheduler.

Hardware-accelerated computing system

A thread management circuit of a processing system stores a thread identifier table and a thread completion table. The thread management circuit receives, from a processor core, a request for execution of a portion of an application by an accelerator circuit. The thread management circuit allocates a thread identifier available in the thread identifier table to the processor core for the execution of the portion by the accelerator circuit. The thread management circuit communicates a response and an acceleration request, both including the allocated thread identifier, to the processor core and the accelerator circuit, respectively. The thread management circuit communicates a thread joining response to the processor core based on a received thread joining request and an indication by the thread completion table that the execution of the portion by the accelerator circuit is complete. The executed portion is integrated with the application based on the thread joining response.

Method and system for accelerator thread management

A technique for operating a system including a plurality of processors and a shared resource includes executing a first instruction by a first processor of the plurality of processors. The first instruction generates a reservation of the shared resource for the first processor. The technique includes, after generating the reservation of the shared resource for the first processor, executing a spin lock by the first processor until successful execution of a second instruction acquires a lock of the shared resource. The technique includes disabling interrupts of the first processor in response to an indicator of the successful execution of the second instruction. The first instruction may be a load and reserve instruction and the second instruction may be a conditional store instruction.

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Gurgaon, India

Sneha Mishra