Iberium Communications Inc.

Other

Sun Microsystems, Inc.

Slobodan Simovich

Thomas J Endres

Stephen Biracree

Anand M Shah

Raúl Alejandro Casas

W Leo Hoarty

Raul Alejandro Casas

Marc E Levitt

Wonzoo Chung

Ramachandra P Kunda

Srinivas Nori

The current application is directed to maintaining the correct number of symbols in a protocol frame in a digital communications receiver, to prevent catastrophic failure due to dynamic multipath or cycle slips. Timing recovery and framing are coherent, facilitated by placing channel estimation directly into a larger timing recovery loop.

Coherent synchronization and framing in a digital television receiver

Certain embodiments of the present invention encapsulate a variety of data, for example, FIC data, together with ATSC-M/H Service data, into a single IP stream, to simplify the interface between demodulator and media processor. A single data interface protocol within the receiver can then be used, facilitating integration.

Simplified data interface protocol for digital television receiver

The present invention is related to joint trellis decoding and equalization using a decision feedback equalizer.

Method and apparatus for joint decoding and equalization

Methods and apparatus for remote antenna subsystems that are physically isolated from receiver subsystems are disclosed. The communication between the two subsystems uses remote communication links. The remote communication links are either wireless, in which case they are designed for indoor low power communications, or are wired, using existing infrastructure in the household such as the power lines. Partitioning between the antenna and receiver subsystems is selectable.

Remote antenna and local receiver subsystems for receiving data signals carried over analog television

A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.

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San Francisco, CA, United States of America

Slobodan Simovich