Bull Hn Information Systems, Inc.

Sleiman Chamoun

Russell Wayne Guenthner

Clinton B Eckard

Bruce E Flocken

Jeffrey D Weintraub

In order to efficiently recover from a processing error in a central processing trait (CPU) incorporating a cache memory and a basic processing unit, the BPU is provided in duplicate, and all BPU data manipulation operations are performed redundantly. After duplicate data has been obtained from the cache memory and manipulated by the duplicate BPUs, the outputs from the duplicate BPUs are placed on respective master (MRB) and slave (SRB) result busses which are coupled to the cache unit where the results are compared for identity. If the results are not identical, a local error signal is issued. In response to the error signal, the corrupted data is stored into cache, but, before the cache is deliberately frozen, the data is restored again using a segment of the original data withdrawn from the cache memory by the BPUs such that, when the cache is frozen in anticipation of remedial action, the data block whose modification took place during the faulting operation will have been restored to its preprocessing condition. As a result, restart, if possible, can commence at the same point in the process rather than at an earlier point.

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Tempe, AZ, United States of America

Sleiman Chamoun