Intel Corporation

Slawomir Grajewski

Prasoonkumar Surti

Abhishek R Appu

Joydeep Ray

Altug Koker

Balaji Vembu

Travis T Schluessler

Jonathan Kennedy

Abhishek Venkatesh

Gabor Liktor

Jeffery S Boles

Subramaniam M Maiyuran

Murali Ramadoss

Karthik Vaidyanathan

Kai Xiao

Ankur N Shah

Devan Burke

Tomasz Janczak

Guei-Yuan Lueh

Michael Apodaca

Elmoustapha Ould-Ahmed-Vall

Sanjeev S Jahagirdar

Kamal Sinha

Nikos Kaburlasos

Adam T Lake

Linda L Hurd

Kiran Chand Veernapu

David M Puffer

John H Feit

Jacek Kwiatkowski

Wenyin Fu

Josh B Mastronarde

Bhushan M Borole

Eric J Hoekstra

Eric J Asperheim

Atsuo Kuwahara

Hugues Labbe

Andrew T Lauritzen

Sameer Kp

David M Cimini

Louis Feng

Zack Waters

Jason M Surprise

Kaiyu Chen

Mike Apodaca

Jeffrey S Boles

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

Cloud based distributed single game calculation of shared computational work for multiple cloud gaming client devices

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Order independent asynchronous compute and streaming for graphics

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

Multi-resolution image plane rendering within an improved graphics processor microarchitecture

An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.

Graphics processor with tiled compute kernels

Apparatus and method for resilient interface for updating a graphics processor. For example, one embodiment of an apparatus comprises a graphics processor; and a configuration memory of the graphics processor to be subdivided into a plurality of configuration regions associated with a corresponding plurality of graphics pipeline stages and/or functional units, wherein a host processor executing a graphics driver is to submit a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of the configuration memory and configuration data to be used to modify at least one configuration region associated with the at least one logical memory address, and wherein the logical memory address is to be used to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units, the at least one configuration region to be responsively updated.

Interface apparatus and method resilient to graphics hardware changes

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.

A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate re-use of register data by partitioning a first part and a second part, the first part to include thread-independent code and the second part to include thread-dependent code.

Graphics processor register data re-use mechanism

Growing community of inventors

Gdansk, Poland

Slawomir Grajewski