Mitsubishi Denki Kabushiki Kaisha

Sizuo Morizane

Hirofumi Nakano

Atsushi Miyanishi

A memory core of a semiconductor data storing circuit device in a semiconductor chip is composed of a memory cell array having memory cells of rows and columns, data input/output circuits of a normal operation in which a data input line and a data output line for one bit of data are arranged at every four columns of the memory cell array, and checking circuits of a test operation in which a test data input line and a test data output line for one bit of test data are arranged at every eight (or two) columns of the memory cell array. In cases where the test data input/output lines for one bit of test data are arranged at every eight columns, because the number of test data input/output lines is lower than the number of data input/output lines, the number of input/output pins for the test operation can be reduced. Also, in cases where the test data input/output lines for one bit of test data are arranged at every two columns, because the number of test data input/output lines is higher than the number of data input/output lines, the number of memory cells simultaneously checked is increased, and a test operation time in the manufacturing of the memory cell array can be shortened.

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Tokyo, Japan

Sizuo Morizane