Qualcomm Incorporated

Siyu Yang

Ashok Swaminathan

Andrew Weil

Dongwon Seo

Shahin Mehdizad Taleie

Behnam Sedighi

Honghao Ji

Negar Rashidi

Jaswinder Singh

Xilin Liu

Sudharsan Kanagaraj

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of current-steering cells, each having a bypass switch, and a resistor ladder circuit having multiple segments. Each segment may include a first resistive element and a second resistive element, the bypass switch being configured to selectively provide a bypass current to a common node between the first resistive element and the second resistive element.

Digital-to-analog converter (DAC) with common-mode correction

An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

Image calibration for time-interleaved digital-to-analog converter

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Siyu Yang