Samsung Electronics Co., Ltd.

Siyoung Choi

Kihyun Kim

Hansoo Kim

Myoungbum Lee

JinGyun Kim

Hoosung Cho

Soodoo Chae

HuiChang Moon

Kihyun Hwang

Jaehun Seo

Myeong-Cheol Kim

Cheol Kyu Kim

Juyul Lee

Seungjae Baik

Kisoo Chang

YooJung Lee

Kwangmin Park

Chanjin Park

Bonyoung Koo

Yong Hoon Son

Toshiro Nakanishi

Byeong Chan Lee

Taek Jung Kim

Juwan Lim

Deok Hyung Lee

In Soo Jung

Jaehoon Jang

Sangjin Hyun

Hoonjoo Na

Kang-Ill Seo

Byung Lyul Park

Sunggil Kim

Hyosan Lee

Hye-Lan Lee

Kyu-ha Lee

Jumyong Park

Hyung-seok Hong

Hagju Cho

Jintae Noh

Hyoungsub Kim

Yugyun Shin

Yi Koan Hong

Jisoon Park

Kinam Kim

Byoungsun Ju

Yongjik Park

Jun-Woong Park

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Nonvolatile memory device and method for fabricating the same

Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Field effect transistor having fin base and at least one fin protruding from fin base

Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone.

Wafer loaders having buffer zones

Field effect transistor having fin base and at lease one fin protruding from fin base

Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on the electrically insulating layer. A string selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. A ground selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate.

Three-dimensional non-volatile memory devices having highly integrated string selection and sense amplifier circuits therein

A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer.

Nonvolatile memory devices including deep and high density trapping layers

Growing community of inventors

Seongnam-si, South Korea

Siyoung Choi