Nxp B.v.

Nxp Usa, Inc.

Siyaram Sahu

Anand Kumar Sinha

Krishna Thakur

Ateet Omer

Vishwajit Babasaheb Bugade

Harish Eleendram

Nagaraju Sunkara

A clock generator includes a buffer stage to drive an output clock and a slew accelerator circuit to receive a first clock signal and generate an input clock signal to the buffer stage. The slew accelerator circuit includes first, second, and third inverter stages. The first stage generates a pair of non-overlapping clock signals from the first clock signal. A rise time of a first non-overlapping clock signal of the pair is faster than a rise time of a second non-overlapping clock signal of the pair, and a fall time of the second non-overlapping clock signal is faster than a fall time of the first non-overlapping clock signal. The second stage generates a first intermediate clock signal based on the pair of non-overlapping clock signals. The third stage generates the input clock signal to the buffer stage based on the first intermediate clock signal and the pair of non-overlapping clocks.

Integrated circuit for clock generation

Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Controlled application of hysteresis in crystal oscillator circuits

A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.

Phase shifted clock generator

A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.

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Siyaram Sahu