Expedera, Inc.

Integrated Device Technology, Inc.

Siyad Chih-Hua Ma

Shang-Tse Chuang

Sharad Vasantrao Chole

Chao-Wen Iseng

Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is an extremely computationally intensive field such that performing artificial intelligence calculations can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence applications can be performed in parallel such that specialized linear algebra matrix processors can greatly increase computational performance. But even with linear algebra matrix processors; performance can be limited due to complex data dependencies. Without proper coordination, linear algebra matrix processors may end up idle or spending large amounts of time moving data around. Thus, this document discloses methods for efficiently scheduling linear algebra matrix processors.

Method and apparatus for scheduling matrix operations in digital processing systems

Artificial intelligence is an increasingly important sector of the computer industry. One of the most important applications for artificial intelligence is object recognition and classification from digital images. Convolutional neural networks have proven to be a very effective tool for object recognition and classification from digital images. However, convolutional neural networks are extremely computationally intensive thus requiring high-performance processors, significant computation time, and significant energy consumption. To reduce the computation time and energy consumption a 'cone of dependency' and “cone of influence” processing techniques are disclosed. These two techniques arrange the computations required in a manner that minimizes memory accesses such that computations may be performed in local cache memory. These techniques significantly reduce the time to perform the computations and the energy consumed by the hardware implementing a convolutional neural network.

Feature extraction with a convolutional neural network

Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is extremely computationally intensive field such that it can be expensive, time consuming, and energy consuming. Fortunately, many of the calculations required for artificial intelligence can be performed in parallel such that specialized processors can greatly increase computational performance. Specifically, artificial intelligence generally requires large numbers of matrix operations to implement neural networks such that specialized Matrix Processor circuits can improve performance. But a neural network is more than a collection of matrix operations; it is a set of specifically coordinated matrix operations with complex data dependencies. Without proper coordination, Matrix Processor circuits may end up idle or spending large amounts of time loading in different weight matrix data. Thus this document discloses apparatus and methods for organizing and controlling multiple Matrix Processor circuits efficiently.

Systems and processes for organizing and controlling multiple matrix processor circuits

Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is very computationally intensive field. Fortunately, many of the required calculations can be performed in parallel such that specialized processors can greatly increase computation performance. In particular, Graphics Processor Units (GPUs) are often used in artificial intelligence. Although GPUs have helped, they are not ideal for artificial intelligence. Specifically, GPUs are used to compute matrix operations in one direction with a pipelined architecture. However, artificial intelligence is a field that uses both forward propagation computations and back propagation calculations. To efficiently perform artificial intelligence calculations, a symmetric matrix processing element is introduced. The symmetric matrix processing element can perform forward propagation and backward propagation calculations just as easily. Furthermore, both of these calculations can be performed without reloading weight matrix values.

Methods and apparatus for constructing digital circuits for performing matrix operations

Artificial intelligence is an increasingly important sector of the computer industry. One of the most important applications for artificial intelligence is object recognition and classification from digital images. Convolutional neural networks have proven to be a very effective tool for object recognition and classification from digital images. However, convolutional neural networks are extremely computationally intensive thus requiring high-performance processors, significant computation time, and significant energy consumption. To reduce the computation time and energy consumption a 'cone of dependency' and 'cone of influence' processing techniques are disclosed. These two techniques arrange the computations required in a manner that minimizes memory accesses such that computations may be performed in local cache memory. These techniques significantly reduce the time to perform the computations and the energy consumed by the hardware implementing a convolutional neural network.

Method and apparatus for efficiently processing convolution neural network operations

A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed sufficient to fully test the memory cells, identifying faulty memory cells in the tested portion of the memory; writing an error map in another portion of the memory, the error map indicating the location of faulty memory cells found in the tested portion and, after executing the test routine and writing the error map, repairing at least some of the faulty memory cells using the error map. Once one portion of memory is tested, another portion is tested and a prior tested portion is used to write a new error map. Repairing, by analyzing the error map, is done at a slower speed than required for memory testing, allowing the use of a smaller logic section in the integrated circuit.

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Palo Alto, CA, United States of America

Siyad Chih-Hua Ma