Faraday Technology Corporation

Arm Limited

Agere Systems Inc.

Sivaramakrishnan Subramanian

Hussainvali Shaik

Nidhir Kumar

Sridhar Cheruku

Ko-Ching Chao

Venkat Rao Vallapaneni

Nirav Patel

Sireesha Tulluri Lakshmi Naga Venkata Srujana

Raghunatha Reddy Lakki Reddy

Eswar Reddi

Youang Pin Chen

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

Memory physical layer interface, memory apparatus and method thereof

A voltage regulator provides a regulated voltage to a double data rate (DDR) Physical Interface (PHY) including a plurality of delay elements. The voltage regulator includes: an amplifier, for receiving a voltage at a first input terminal and generating an output voltage; a first MOSFET coupled to a supply voltage and a second input terminal of the amplifier; a second MOSFET coupled in parallel with the first MOSFET for generating a first current in response to a first enable signal; a load, coupled to the first MOSFET and the second MOSFET, for generating the regulated voltage; and a load capacitor, coupled in parallel with the load. The first enable signal is generated by inputting a gate enable signal for a delay element of the plurality of delay elements into a delay circuit corresponding to the delay element.

Voltage regulator to prevent voltage drop in regulated voltage for double data read physical interface

The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.

Physical interface and associated signal processing method for clock domain transfer of quarter-rate data

A calibratable delay chain having a delay chain and an adjustment circuitry varying a delay of each of the plurality of delay stages in the chain. The calibration circuitry is configured to calibrate a delay of the delay chain. The calibration circuitry includes calibration control circuitry for controlling the calibration and supplying the input value to an adjustment circuitry. Output selection circuitry is provided to select an output from a predetermined point along the delay chain. A bypass path bypasses the delay chain and a digital comparator compares an output from the delay chain and an output from the bypass path. An analogue comparator compares an output from the delay chain and an output from the bypass path. The calibration control circuitry is configured to control the output selection circuitry to output a signal from one point on the delay chain to the digital comparator.

Calibration of delay chains

Calibration circuitryfor an off-chip driver circuitand/or an on-die termination circuitis provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistoris then used to determine which of the N-bit calibration values produces a combined impedance closest to the designed threshold impedance.

Reduced quantization error I/O resistor calibrator

A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least one power ring. The step of determining a location of at least one connection between the ESD structure and at least one power ring may include the steps of determining a minimum spanning tree of elements associated with a given power ring; and back-tracing through a minimum spanning tree of elements associated with a given power ring in order to determine a minimal list of routed paths among the elements.

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Bengaluru, India

Sivaramakrishnan Subramanian