Adv Antest Corporation

Sivanarayana Pandian Rajadurai

Preet Paul Singh

Alan S Krech, Jr

Edmundo De La Puente

Darrin Paul Albers

Andrew Chan

An automated test equipment (ATE) system comprises a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The FPGA is communicatively coupled to the tester processor, wherein the FPGA is configured to internally generate commands and data transparently from the tester processor for testing a DUT. Further, the system comprises a demultiplexer positioned between the DUT and the FPGA, wherein, responsive to a determination that the DUT is operating in a high speed mode, the demultiplexer is configured to channel data traffic from the DUT to a Serializer/Deserializer (SerDes) receiver on the FPGA, and further wherein, responsive to a determination that the DUT is operating in a low speed mode, the demultiplexer is configured to channel data traffic from the DUT to input buffers on the FPGA with switchable on/off input terminations.

Method and apparatus for providing UFS terminated and unterminated pulse width modulation support using dual channels

A method for receiving data using an FPGA receiver circuit comprises receiving payload data from a DUT using a first rate of a plurality of line rates during a first burst, wherein the DUT is communicatively coupled to the FPGA receiver circuit. The method further comprises transitioning to a power saving state at an end of the first burst and receiving synchronization data from the DUT using a second rate of a plurality of line rates during a second burst. Further, the method comprises establishing synchronization with a clock data recovery (CDR) circuit of the FPGA receiver circuit at the second rate and receiving payload data from the DUT at the second rate.

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San Jose, CA, United States of America

Sivanarayana Pandian Rajadurai