International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Lam Research Corporation

Globalfoundries Inc.

Tessera LLC

Infineon Technologies Ag

Renesas Electronics Corporation

Elpis Technologies Inc.

Sivananda K Kanakasabapathy

Fee Li Lie

Sean David Burns

Stuart A Sieg

Kangguo Cheng

Lawrence Alfred Clevenger

Christopher J Penny

Gauri V Karve

Nicole A Saulnier

Hong He

Hemanth Jagannathan

Bruce Bennett Doris

Matthew Earl Colburn

Roger Allan Quon

Tenko Yamashita

Theodorus E Standaert

Nelson M Felix

Peng Xu

John Ryan Sporre

Huiming Bu

Veeraraghavan S Basker

Andrew Mark Greene

Yann A M Mignot

Su Chen Fan

Babar Ali Khan

Effendi Leobandung

Kevin K Chan

Yunpeng Yin

Michael C Gaidis

Xinhui Wang

Masaharu Kobayashi

Balasubramanian Pranatharthiharan

Alexander Reznicek

Dechao Guo

Soon-Cheon Seo

Ekmini Anuja De Silva

Juntao Li

David V Horak

Ruqiang Bao

Zhenxing Bi

Injo Ok

Richard Stephan Wise

Eric R Miller

Solomon Assefa

Takashi Ando

Junli Wang

Sanjay C Mehta

David William Abraham

Rajasekhar Venigalla

Emre Alptekin

Allen H Gabor

Ahmet Serkan Ozcan

Balasubramanian S Haran

Donald Francis Canaperi

David Lee Rath

Johnathan E Faltermeier

John Christopher Arnold

Byeong Yeol Kim

Yang Pan

Brent A Anderson

Karthik Balakrishnan

Keith E Fogel

Eugene John O'Sullivan

Chun Wing Yeung

Indira P Seshadri

Chiahsun Tseng

Hui-Jung Wu

Raghavasimhan Sreenivasan

Chih-Chao Yang

Josephine B Chang

Charles W Koburger, Iii

Ying Di Zhang

Andres Bryant

Geng Wang

Adrien Lavoie

Qinghuang Lin

Pranita Kulkarni

Vamsi Krishna Paruchuri

Sean Teehan

Matthew Warren Copel

Richard Alan Gottscho

Chanro Park

Vijay Narayanan

Shom Ponoth

Elbert Emin Huang

Ravikumar Ramachandran

Chi-Chun Liu

Eduard Albert Cartier

Renee Tong Mo

Kafai Lai

Yongan Xu

Viraj Yashawant Sardesai

Kathryn Turner Schonenberg

Samantha SiamHwa Tan

Philip Louis Trouilloud

Michael F Lofaro

Nicholas C M Fuller

Huimei Zhou

Ankit Vora

Gen Tsutsui

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

Integrated dry processes for patterning radiation photoresist patterning

Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by patterning a tin oxide layer using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry, and using patterned photoresist as a mask, thereby providing a substrate having a plurality of protruding tin oxide features (mandrels). Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrels. Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning underlying layers on the substrate.

Tin oxide mandrels in patterning

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Structure and process to tuck fin tips self-aligned to gates

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Self aligned pattern formation post spacer etchback in tight pitch configurations

Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.

Chamfer-less via integration scheme

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Forming a sacrificial liner for dual channel devices

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Self-aligned pattern formation for a semiconductor device

Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by providing a substrate having a plurality of protruding tin oxide features (mandrels) residing on an exposed etch stop layer. Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrel (e.g., leaving at least 50%, such as at least 90% of initial height at the sidewall). Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning the etch stop layer and underlying layers.

The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.

Fin cut to prevent replacement gate collapse on STI

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Additive core subtractive liner for metal cut etch processes

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Growing community of inventors

Niskayuna, NY, United States of America

Sivananda K Kanakasabapathy