Xilinx, Inc.

Sivakumar Velusamy

Jorge Ernesto Carrillo

Satish R Ganesan

Navaneethan Sundaramoorthy

Ralph D Wittig

Amit Kasat

Raj Kumar Nagarajan

Vasanth Asokan

A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.

Coprocessor interface architecture and methods of operating the same

Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to execute a plurality of instructions one or more times. The target processor provides state data at the trace port and to the input port of the bus. A profile circuit arrangement is coupled to the output port of the first bus, and a memory is coupled to the profile circuit arrangement. The profile circuit arrangement is configured to read data from the output port of the first bus and write the data to the memory.

Circuit arrangement for profiling a programmable processor connected via a uni-directional bus

A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.

Framework for cycle accurate simulation

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Los Gatos, CA, United States of America

Sivakumar Velusamy