Seagate Technology Incorporated

Sivakumar Sambandan

Earl T Cohen

Jackson L Ellis

Stephen D Hanna

Jeonghun Kim

Cache coherency of a global address space of a cache can be maintained with one or more tier control units (TCUs). The global address space of the cache may be shared by multiple domains. Domains may include multiple controllers and a local interconnect operatively coupling the controllers to the cache. The local interconnect of each domain may maintain a cache coherency of a local address space of the cache shared by the controllers of the domain. The one or more TCUs may be operatively coupled to the local interconnects of the domains to maintain the cache coherency of the global address space.

Systems and methods for maintaining cache coherency

A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.

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Pune, IN, United States of America

Sivakumar Sambandan