Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Marvell Asia Pte., Ltd.

Sivakumar Radhakrishnan

Sin Sim Tan

Mark A Schmisseur

Sujoy Sen

Kenneth C Creta

William T Futral

Pankaj Kumar

Gregory Cummings

David C Lee

Kenneth C Haren

Michael T Klinglesmith

Bradley A Burres

Malay Trivedi

Eric Dahlen

Thomas M Slaight

Brian M Leitner

Geetani R Edirisooriya

Marc Tim Jones

Matthew R Wilcox

Saptarshi Mondal

Siva Balasubramanian

Vinodh Gopal

Wajdi K Feghali

Stephan Jourdan

Mahesh S Natu

Lily Pao Looi

Suneeta Sah

Thomas C Brown

Jayasekhar Tholiyil

Altug Koker

Rajat Agarwal

Ashok Raj

Srikanth T Srinivasan

Rabin Sugumar

Howard S David

Narayan Ranganathan

Jed D Griffin

Zhenyu Zhu

Bruce A Tennant

William Harry Nale

Anand K Enamandram

Marc A Goldschmidt

Chet R Douglas

Tina C Zhong

Yi-Feng Liu

Erik A McShane

Dan J Williams

Vishal Verma

Scott R Rushford

Michael J Wiznerowicz

Jasper Balraj

Ham Prince

Rami A Naqib

Chris Ruffin

Peter Molnar

Kapilan Maheswaran

Roger W Liu

David J Hotz

Steve Kulick

Randall L Albion

Gregory D Cummings

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Presentation of direct accessed storage under a logical drive model

A circuit provides for processing and routing peer-to-peer (P2P) traffic. A bus request queue store a data request received from a first peer device. A decoder compares an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory. A bus interface unit, in response to the data request being directed to the second peer device, 1) generates a memory access request from the bus request and 2) transmits the memory access request toward the second peer device via a bus. A memory controller, in response to the data request being directed to a local memory, accesses the local memory to perform a memory access operation based on the data request.

Scalable peer to peer data routing for servers

An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

Logging errors in error handling devices in a system

Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

Micro-architectural techniques to minimize companion die firmware loading times in a server platform

Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

Systems and devices having a scalable basic input/output system (BIOS) footprint and associated methods

In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

Offload data transfer engine for a block data transfer interface

Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

Enhanced cyclical redundancy check circuit based on galois-field arithmetic

Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.

Dynamic and idle power reduction sequence using recombinant clock and power gating

A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Method and apparatus for increasing data reliability for raid operations

Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.

Methods and apparatuses for flushing write-combined data from a buffer

In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Dynamic squelch detection power control

Growing community of inventors

Portland, OR, United States of America

Sivakumar Radhakrishnan