Adaptec, Inc.

Sivakumar Munnangi

Anil Kapatkar

Srinivasan Venkataraman

Ramkumar Jayam

Shridhar K Mukund

Todd Sperry

Purna Chandra Mohanty

Jignesh Raval

A network node is disclosed. The network node includes a host processor. The network node also includes an integrated circuit. The integrated circuit includes a hardware portion configured to perform a first set of TCP acceleration tasks that require a first speed level. The integrated circuit also includes a network protocol processor configured to perform a second set of TCP acceleration tasks that require a second speed level, which is lower than the first speed level. The integrated circuit further includes an embedded processor configured to perform a third set of TCP acceleration tasks that require a third speed level, which is lower than the second speed level. The network node further includes a plurality of data paths configured to couple the integrated circuit to the host processor, the plurality of data paths being implemented based on different protocols.

Systems and methods for implementing host-based security in a computer network

A method in a target device for partially reordering a plurality of data packets transmitted from a source device. The source device is coupled to the target device via a computer network. The method receiving a first set of data packets from the transmitted device, and ascertaining whether the first set of data packets represents a set of data packets that the target device expects to receive next. If the first set of data packets does not represents the set of data packets that the target expects to receive next, the method includes storing the first set of data packets in a memory buffer of the target device. The storing includes arranging the first set of data packets in the memory buffer such that data packets in the memory buffer, including the first set of data packets, are in order in the memory buffer.

Methods and apparatus for partially reordering data packets

An architecture for implementing host-based security such that data security may be applied whenever the confidential data leaves a host computer or a networked device. The improved method and architecture may be implemented in a single integrated circuit for speed, power consumption, and space-utilization reasons. Within the integrated circuit, a combination of hardware-implemented, network processor-implemented, and software-implemented functions may be provided. The innovative host-based security architecture may offer line-rate IPSec acceleration, TCP acceleration, or both.

A method for receiving receive data associated with a bi-directional data flow between a first host computer and a second host computer. The first host computer and the second host computer are coupled via a computer network. The method includes storing receive-facilitating parameters employed for the receiving the receive data in a first control block. The first control block is implemented in the first host computer and associated with the bi-directional data flow. The receiving the receive data is performed in accordance with the TCP protocol. The method also includes employing the receive-facilitating parameters in the first control block to facilitate receiving a given portion of the receive data at the first host computer from the second computer. In accordance with this embodiment of the invention, the receiving the given portion of the receive data occurs simultaneously with servicing a transmit request pertaining to transmit data associated with the bi-directional data flow from the first host computer to the second host computer. The transmit data is transmitted using transmit-facilitating parameters stored in a second control block implemented in the first host computer. The transmit data is transmitted in accordance with the TCP protocol.

Apparatus and methods for receiving data at high speed using TCP/IP

The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit ('ASIC') chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol ('TCP/IP') processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.

Method and system for verifying the hardware implementation of TCP/IP

The present invention provides for a method and protocol for high bandwidth, low-latency and reliable transfer of variable length FC Frames over the Gigabit Ethernet.

Protocol stack for linking storage area networks over an existing LAN, MAN, or WAN

A method for exchanging data in a first host computer coupled to a network. The network is also coupled to a second host computer. The method includes employing a first Transmit Control Block (Tx TCB) to facilitate transmitting first data associated with a bi-directional data flow from the first host computer to the second host computer. The first data is transmitted using the TCP protocol. The first Tx TCB is associated with the first host computer and is configured for storing transmit-facilitating parameters associated with the transmitting the first data using the TCP protocol. The method also includes employing a first Receive Control Block (Rx TCB) to facilitate receiving second data associated with the bi-directional data flow. The second data is transmitted from the second host computer to the first host computer using the TCP protocol. The first Rx TCB is associated with the first host computer and is configured for storing receive-facilitating parameters associated with the receiving the second data using the TCP protocol. In accordance with this embodiment of the invention, the first Tx TCB and the first Rx TCB are employed to simultaneously service a transmit request pertaining the first data and a receive request pertaining the second data.

Systems and methods for high speed data transmission using TCP/IP

A method for transmitting transmit data associated with a bi-directional data flow between a first host computer and a second host computer. The first host computer and the second host computer are coupled via a computer network. The method includes storing transmit-facilitating parameters employed for the transmitting the transmit data in a first control block. The first control block is implemented in the first host computer and associated with the bi-directional data flow. The transmitting the transmit data is performed in accordance with the TCP protocol. The method also includes employing the transmit-facilitating parameters in the first control block to facilitate servicing a transmit request pertaining to a given portion of the transmit data from the first host computer to the second computer. In accordance with this embodiment of the invention, the servicing the transmit request occurs simultaneously with servicing a receive request pertaining to receive data associated with the bi-directional data flow from the second host computer by the first host computer. The receive data is received using receive-facilitating parameters stored in a second control block implemented in the first host computer. The receive data is received in accordance with the TCP protocol.

Growing community of inventors

Santa Clara, CA, United States of America

Sivakumar Munnangi