Synopsys, Inc.

Sivakumar Arulanantham

Prashant Gupta

Sanjiv Mathur

Chun-Cheng Chi

Shih-Pin Hung

Srinivasan Krishnamurthy

Shibaji Banerjee

Prakasha Karkada Holla

Anusha Reddy Sindhwala

Ashima Sahil Dabare

A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.

Clock re-convergence pessimism removal through pin sharing during clock tree planning

Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.

Automated balanced global clock tree synthesis in multi level physical hierarchy

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Hillsboro, OR, United States of America

Sivakumar Arulanantham