International Business Machines Corporation

Siva Sundar A

Shakti Kapoor

Manoj Dusanapudi

Preetham M Lobo

Vinod Bussa

Brenton Yiu

Gaurav Sulagodu Venkatagiri

Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.

Processing data in memory using an FPGA

In an approach to validation of correctness of interrupt triggers and delivery a computer allocates one or more flags of a gang of flags. The computer allocates one or more interrupt source numbers, wherein each interrupt source number of the one or more interrupt source numbers corresponds to a flag of the gang of flags. The computer allocates one or more virtual processors to process the one or more interrupt source numbers. The computer schedules the one or more virtual processors. The computer receives one or more interrupt triggers corresponding to the one or more interrupt source numbers. The computer updates the one or more flags corresponding to the one or more received interrupt triggers. The computer determines whether all of the one or more flags in the gang of flags is updated. The computer determines a lost interrupt source number.

Validation of correctness of interrupt triggers and delivery

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Bengaluru, India

Siva Sundar A