Infineon Technologies Ag

Qimonda Ag

Polaris Innovations Limited

Siva RaghuRam

Simon Muff

Hermann Ruckerbauer

Georg Braun

Maksim Kuzmenka

Abdallah Bacha

Josef Schuster

A semiconductor memory module () includes a circuit substrate (), a first (), a second (), a third () and a fourth () rank of memory chips (), a first register () and a second register (). The first register () and the second register () each comprise a first input () for receiving a respective chip select signal (CSCS), a second input () for receiving a respective other chip select signal (CSCS) at least one third input () for receiving command/address signals (CA), and at least one third output (). The at least one third output () of the respective first () and second () register transmits the command/address signals (CA), if at least one of the respective chip select signal (CSCS) received at the respective first input () of the respective register () and the respective other chip select signal (CSCS) received at the respective second input () of the respective register () is active, and blocks a transmission of the command/address signals (CA), if both the respective chip select signal (CSCS) received at the respective first input () of the respective register () and the respective other chip select signal (CSCS) received at the respective second input () of the respective register () are inactive.

Semiconductor memory module, electronic apparatus and method for operating thereof

The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.

Memory arrangement

In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a connector strip, which runs at a first edge of the at least one outer face in a first direction and has a multiplicity of electrical contacts that are lined up in the first direction. The printed circuit board extends in the first direction between two opposite second edges. At least nine of the semiconductor chips of the same type are respectively mounted next to one another on the outer face of the printed circuit board between the center of the printed circuit board and the respective second edge of the printed circuit board. The semiconductor chips of the same type respectively have a smaller dimension and, in the direction perpendicular to the smaller dimension, a larger dimension that is larger than the smaller dimension. A respective first group of four of the semiconductor chips of the same type, which are oriented so as to have their shorter dimension parallel to the connector strip, is arranged at the respective second edge of the printed circuit board. A second group of five semiconductor chips of the same type is respectively arranged between the first group of semiconductor chips and the center of the printed circuit board. The first group of semiconductor chips and the second group of semiconductor chips are actuated by two separate line buses whose conductor tracks branch toward all the semiconductor chips in the respective group of semiconductor chips.

Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type

A circuit board arrangement includes a heat dissipater. A cooling body is arranged near a first circuit board and a second circuit board. Both circuit boards have electronic devices on two major surfaces. The cooling body is arranged between the electronic devices on one surface of the first circuit board and the electronic devices on one surface of the second circuit board. The circuit boards are supported by fixing elements of the cooling body.

Circuit board arrangement including heat dissipater

A semiconductor memory module () includes a circuit substrate (), a first (), a second (), a third () and a fourth () rank of memory chips (), a first register () and a second register (). The first register () and the second register () each comprise a first input () for receiving a respective chip select signal (CS, CS), a second input () for receiving a respective other chip select signal (CSCS) at least one third input () for receiving command/address signals (CA), and at least one third output (). The at least one third output () of the respective first () and second () register transmits the command/address signals (CA), if at least one of the respective chip select signal (CS, CS) received at the respective first input () of the respective register () and the respective other chip select signal (CSCS) received at the respective second input () of the respective register () is active, and blocks a transmission of the command/address signals (CA), if both the respective chip select signal (CS, CS) received at the respective first input () of the respective register () and the respective other chip select signal (CSCS) received at the respective second input () of the respective register () are inactive.

Semiconductor memory module and electronic apparatus including a semiconductor memory module and method for operating thereof

A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.

Memory module, memory extension memory module, memory module system, and method for manufacturing a memory module

A chip stack employing BGA or FBGA integrated circuit chip packages is provided. Two chip packages have bottom surfaces attached with sets of electrical contacts, which are oriented towards each other and are electrically connected to conductive patterns formed within the same flex substrate. One set contacts a conductive pattern on a top surface, the other set contacts a pattern on a bottom surface of the flex substrate within a same end portion. The other end portion has a conductive pattern, and is connected to a third set of electrical contacts. The flex substrate is wrapped around an edge of the chip package to connect the third set with the other two sets. Thereby, four chip packages are provided with this design, the layout of conductive traces formed within at least one of the flex substrates is meandered to compensate for length differences with respect to the other flex substrate.

Chip stack employing a flex circuit

The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).

Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)

A stacked DRAM memory chip for a Dual In Line Memory Module (DIMM) is disclosed. According to one aspect, the DRAM memory chip comprises at least four stacked DRAM memory dies. Further, the memory dies are each selectable by a corresponding internal memory rank signal. Each memory die comprises an array of memory cells. A common internal address bus is provided for addressing the memory cells and is connected to all stacked DRAM memory dies. Internal data buses are provided for writing data into the memory cells and reading data out of the memory cells of the DRAM memory dies. An integrated redriving unit comprises buffers for all internal address lines provided for driving external address signals applied to address pads of the DRAM memory chip. A multiplexer/demultiplexer switches the internal data lines of the selected DRAM memory die. A memory rank decoder selects a corresponding memory die.

Growing community of inventors

Germering, Germany

Siva RaghuRam