Globalfoundries U.S. Inc.

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Siva P Adusumilli

Mark Levy

Steven M Shank

Anthony K Stamper

John J Ellis-Monaghan

Vibhor Jain

Johnatan A Kantarovsky

Ramsey M Hazbun

Alvin Jose Joseph

Yves T Ngu

Rajendran Krishnasamy

Jeonghyun Hwang

Michael Joseph Zierak

Yusheng Bian

Cameron E Luce

Ian McCallum-Cook

Sebastian Theodore Ventrone

Steven J Bentley

Michel J Abou-Khalil

Uzma B Rana

Ajay Raman

Ruilong Xie

Laura J Schutz

Julien Frougier

Jagar Singh

Sunil Kumar Singh

Bruce Walter Porth

Ephrem G Gebreselasie

Mickey H Yu

Brett T Cucci

Laura J Silverstein

Joshua Dillon

Spencer H Porter

Kangguo Cheng

Edward J Nowak

Hui Zang

Chanro Park

Ajey Poovannummoottil Jacob

John H Zhang

Qizhi Liu

Min Gyu Sung

Xusheng Kevin Wu

Jiehui Shu

Haigou Huang

Edward William Kiewra

Murat Kerem Akarvardar

Yi Qi

Richard A Phelps

Kenneth John Giewont

Sen Liu

Pietro Montanini

Steven R Soss

Bo Peng

Aaron Vallett

Pernell Dongmo

Robinhsinku Chao

Andre Sturm

Bojidha Babu

Mark Goldstein

Claire E Kardos

Fuad H Al-Amoody

Felix P Anderson

Yves Ngu

Mark David Levy

A photodetector structure includes a first semiconductor material layer over a doped well in a substrate. The photodetector structure includes an air gap vertically between the first semiconductor material layer and a first portion of the doped well. The photodetector structure includes an insulative collar on the first portion of the doped well and laterally surrounding the air gap. The photodetector structure may include a second semiconductor material layer on the first portion of the doped well and laterally surrounded by the insulative collar. The photodetector structure may include a third semiconductor layer over the first semiconductor layer.

Photodetector structure with air gap and related methods

Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation

A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.

Semiconductor structure with frontside port and cavity features for conveying sample to sensing element

Structures for a waveguide and methods of forming a waveguide. The structure comprises a substrate, a waveguide core comprising a compound semiconductor material, and a layer disposed on the substrate. The layer comprises the compound semiconductor material, and the layer includes a cavity positioned beneath the waveguide core.

Compound-semiconductor waveguides with airgap cladding

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

High electron mobility transistor devices having a silicided polysilicon layer

Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.

Integration of compound-semiconductor-based devices and silicon-based devices

A photodiode and a related method of manufacture are disclosed. The photodiode includes a transfer gate and a floating diffusion adjacent to the transfer gate. In addition, the photodiode includes an upper terminal; an intrinsic semiconductor region in contact with the upper terminal, the intrinsic semiconductor region in a trench in a substrate adjacent to the transfer gate; and a lower terminal in contact with the intrinsic semiconductor region. An insulator layer is along an entirety of a sidewall of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well may also optionally be between the insulator layer and the transfer gate.

Photodiode with insulator layer along intrinsic region sidewall

Disclosed is a semiconductor structure including a device (e.g., a field effect transistor (FET), a biosensor FET (bioFET) or an ion-sensitive FET (ISFET)) with a fluid-based gate. The structure includes a substrate, an intermediate layer on the substrate, and a semiconductor layer on the intermediate layer. The device includes, within the semiconductor layer, a source region, a drain region, and a channel region between the source and drain regions. The structure includes, for the fluid-base gate, a cavity within the intermediate layer below the channel region and lined with a dielectric liner. Optionally, the exposed surface of the dielectric liner within the cavity is functionalized. Additional dielectric layers are stacked on the semiconductor layer and at least one port extends essentially vertically through the dielectric layers, the semiconductor layer and the dielectric liner to the cavity so as to allow fluid for the fluid-based gate to flow into the cavity.

Field effect transistor with buried fluid-based gate and method

The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

Switches in bulk substrate

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

Field effect transistor with shallow trench isolation features within source/drain regions

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.

Photodiodes

Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

Semiconductor structure including photodiode-based fluid sensor and methods

Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

Semiconductor structure with semiconductor-on-insulator region and method

Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

Transistor with multi-level self-aligned gate and source/drain terminals and methods

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South Burlington, VT, United States of America

Siva P Adusumilli