Globalfoundries U.S. Inc.

Siva Kumar Chinthu

Devesh Dwivedi

Suresh Pasupula

Venkatesh P Gopinath

Sunil Kumar

Kevin A Batson

Lejan Pu

Chunsung Chiang

Palle Sundar Veerendranath

Sundar Veerendranath Palle

Veerendranath P Sundar

Venu Gopal Reddy Ara

Abdul Rajak

Anoop Delampady

Lalit Mohan Dani

Disclosed is a charge pump circuit including: a single primary charge pump stage or multiple primary charge pump stages connected in series; a pass transistor connected between an output node of the primary charge pump stage (or of the last of the multiple primary charge pump stages, if applicable) and an output terminal; and a supplementary charge pump stage. The supplementary charge pump stage receives the same input voltage as the primary charge pump stage (or the same input voltage as the last of the multiple primary charge pump stages, if applicable) and controls the gate of the pass transistor to reduce ripple at the output terminal. A capacitive load can also be connected to the output terminal to reduce ripple and the size of the capacitive load can be selected to achieve a desired balance between the amount of ripple and circuit size.

Charge pump with pass transistor controlled by a supplementary charge pump stage

A pre-driver includes first, second, third, and fourth P-channel field effect transistors (PFETs) with voltage ratings equal to a low first voltage (V). Between power rails at Vand at a higher second voltage (V), the first and third PFETs are series-connected and the second and fourth PFETs are also series-connected. The third and fourth PFETs are cross-coupled. The first and second PFETs have gates that receive a pre-driver input signal (Pin) that switches between Vand ground and an inverted pre-driver input signal (Pinb), respectively. At an output node between the first and third PFETs, the pre-driver outputs a driver input signal (Din) that switches between Vand V. A circuit includes this pre-driver (e.g., connected between a voltage level shifter and a driver or connected between a voltage level shifter and a buffer).

Compact high voltage pre-driver and circuits including the pre-driver

A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.

Voltage level shifter with programmable high supply voltage and high supply voltage-dependent variable low supply voltage

The present disclosure relates to semiconductor structures and, more particularly, to a LDO regulator circuit and methods of manufacture. The structure includes a comparator connected to a first transistor of a low drop-out (LDO) circuit; a second transistor connected to the first transistor; and a feedback loop connected to the first transistor and an output of the LDO circuit.

Low drop-out (LDO) regulator circuit

A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

Multi-stage charge pump circuit including voltage level shifter for clock signal generation

Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2˜½*VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.

Multi-rail sense circuit with pre-charge transistors and memory circuit incorporating the sense circuit

A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

Voltage level shifter with multi-step programmable high supply voltage and high supply voltage-dependent variable low supply and gate bias voltages

Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

Single ended sense amplifier with current pulse circuit

An apparatus includes an amplifier, a pass transistor connected to a load and to an input of the amplifier, and a capacitor connected between the amplifier and the pass transistor.

Low-dropout voltage regulator (LDO) having overshoot/undershoot capacitor

Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.

Level shifter with reduced static power consumption

Disclosed is a multi-stage charge pump. A first stage is controlled by a first clock signal. A second stage is controlled by a second clock signal, which has high and low states that are shifted relative to the high and low states of the first clock signal. The high and low states of the second clock signal can be higher than the high and low states, respectively, of the first clock signal for a positive charge pump and vice versa for a negative charge pump. Any additional stage is similarly controlled by an additional clock signal that is shifted with respect to the clock signal controlling the immediately preceding stage. By shifting the high and low states of clock signals controlling downstream stages, the need for series-connected or high voltage capacitors in the downstream stages is eliminated and circuit complexity and area consumption are reduced.

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Bengaluru, India

Siva Kumar Chinthu