Samsung Electronics Co., Ltd.

Siuchuang Ivan Lu

Sang Won Son

Venumadhav Bhagavatula

Tienyu Chang

Kee-Bong Song

Pranav Dayal

Hou-Shin Chen

Siddharth Seth

Sriramkumar Venugopalan

Anirban Sarkar

Yanru Tang

Sung-En Chiu

Sangwon Son

Pritesh Vora

Samrat Dey

A method, a phase shifter, and a user equipment (UE) are disclosed for transmitting and receiving signals in a phased array. The method includes receiving, by a balun of a phase shifter, a transmission single-ended input signal at a single-ended side of the balun and generating a transmission differential input signal at a differential side of the balun, generating, by a differential quadrature coupler of the phase shifter, a transmission in-phase signal and a transmission quadrature signal, based on the transmission differential input signal, and combining, by a differential attenuator of the phase shifter, the transmission in-phase signal and the transmission quadrature signal into a differential phase-shifted output signal.

Phased array transceiver including a bidirectional phase shifter

Disclosed is a device including a first line, a second line including a first section disposed on a first side of the first line and a second section disposed on a second side of the first line, the second side being opposite to the first side and the second section being separate from the first section by a distance, and at least one bridge electrically connecting an end of the first section with an end of the second section and extending across the first line. The device may be a directional coupler that achieves significantly higher directivity than conventional directional coupler structures, and hence, improves power detection accuracy.

Compact high-directivity directional coupler structure using interdigitated coupled lines

A closed-loop power control (CLPC) system is disclosed that includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes a first power amplifier, a first output power detector configured to detect a first output power level of the first power amplifier, and a first processor configured to determine a first analog gain for a first controller and a first gain for a first digital-to-analog converter based on a first accumulated error between the first output power level and a target Effective Isotropically Radiated Power. A second processor is configured to set a first variable gain of a first variable gain amplifier coupled to an input of the first power amplifier. The CLPC can be configured to control the gain of the first signal path separately or as one signal path.

Distributed closed-loop power control with VGA gain update

A method of gain step calibration by a user equipment (UE) includes selecting, a l th antenna path having a gain Gfor a transmitter (Tx) of the UE and a corresponding m th antenna path having a gain Gfor a receiver (Rx) of the UE; determining, a first loopback signal power for the l th antenna path having the gain Gfor the transmitter (Tx) of the UE and the corresponding m th antenna path having the gain Gfor the receiver (Rx) of the UE; determining, a second loopback signal power for the l th antenna path having a gain G'for the transmitter (Tx) and the corresponding m th antenna path having the gain Gfor the receiver (Rx); and determining, a transmitter gain step of the UE based on the first loopback signal power and the second loopback signal power.

Method and apparatus for loopback gain step calibration on RF chain with phase shifter

An apparatus and method are provided. The apparatus includes a multiplexer, including first, second, and third inputs, and an output; a first transistor, including a gate connected to the multiplexer, and first and second terminals; a first variable capacitor, including a first terminal connected to the first transistor, a second terminal, and an input; a first inductor, including a first terminal connected to the first transistor, and a second terminal connected to the second terminal of the first variable capacitor; a second transistor, including a gate connected to the output of the multiplexer, a first terminal, and a second terminal connected to the second terminal of the first inductor; a second inductor mutually coupled to the first inductor, including a first and second terminals; and a balun-bias switch, including first, second, and third inputs, and an output connected to the second terminal of the second inductor.

Apparatus for and method of programmable matching network for multiple signal types

An apparatus and a method. The apparatus includes passive mixers, wherein each of the passive mixers includes a first input for receiving BB, a second input for receiving, a third input for receiving BB, a fourth input for receiving, a fifth input for receiving a first clock signal with a unique phase shift within one of the passive mixers, a sixth input for receiving a second clock signal with a unique phase shift within one of the passive mixers, a seventh input for receiving a third clock signal with a unique phase shift within one of the passive mixers, an eighth input for receiving a fourth clock signal with a unique phase shift within one of the passive mixers, and at least one output; and a voltage-domain vector summation array connected to the output of each of the passive mixers.

System and method for linearizing a transmitter by rejecting harmonics at mixer output

An apparatus and method are provided. The apparatus includes a multiplexer, including a first input, a second input, a third input, and an output; a first transistor, including a gate, a first terminal, and a second terminal; a first variable capacitor, including a first terminal, a second terminal, and an input; a first inductor, including a first terminal and a second terminal; a second transistor, including a gate, a first terminal, and a second terminal; a second inductor mutually coupled to the first inductor, including a first terminal and a second terminal; a balun-bias switch, including a first input, a second input, a third input, and an output; a second capacitor, including a first terminal, and a second terminal; and a port-switch, including a first input, a second input, a third input, and an output.

Growing community of inventors

San Jose, CA, United States of America

Siuchuang Ivan Lu