Vlsi Technology, Inc.

Vsli Technology, Inc.

Monterey Design Systems, Inc.

Siu-Tong Hui

Sunil V Ashtaputre

Mark R Hartoog

Moazzem M Hossain

Ying-Meng Li

Jacob Greidinger

Dale M Wong

Ara Markosian

Daniel R Brasen

Yaacov (Jacob) Greidinger

Sedrak Sargisian

A system is disclosed for compacting an initial electronic layout of cells within an initial layout boundary. The system includes forming paths extending from a bottom edge of the layout to a top edge. The paths intersect cells of the initial layout. The system determines which of the paths are critical paths. Critical cuts are then determined. A critical cut is a cut that severs critical paths. A set of cells associated with a critical cut are removed from the layout and replaced in order to reduce the initial layout boundary.

Method and apparatus for optimizing electronic design

The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Method and apparatus for making integrated circuits by inserting buffers

The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

A method sizes routing channels used to route pads to a logic core. Six channels are defined. The six channels include a first special channel, a second special channel, a left channel, a right channel, a bottom channel and a top channel. The first special channel is immediately below the logic core and within a span of the logic core. The second special channel is immediately above the logic core and within a span of the logic core. The left channel is adjacent to a left side of the logic core, the first special channel and the second special channel. The right channel is adjacent to a right side of the logic core, the first special channel and the second special channel. The bottom channel is adjacent to a bottom side of the left channel, the first special channel and the right channel. The top channel is adjacent to a top side of the left channel, the first special channel and the right channel. Pads are positioned at a top side of the top channel, at a bottom side of the bottom channel, at a left side of the left channel and at a right side of the right channel. After performing a global route through the six channels, the six channels are re-sized based on channel density resulting from channel routing each of the six channels. The re-sizing includes repositioning the pads.

Improved pad ring router

In a method for placement of components for a VLSI circuit, control signal connection networks and data signal connection networks are identified. Then, an initial placement of the components for the VLSI circuit is made. This initial placement is iteratively improved. The algorithm used for the iterative improvement has a cost metric in which a horizontal component for length of a connection network and a vertical component for length of the connection network are weighted differently dependent on whether the connection network was identified as a control signal connection network or a data signal connection network. The different weighting results in improved regularity of the placement of data path components and thus a more efficient routing of connection networks between the components.

Method for regular placement of data path components in VLSI circuits

In a preplacement method for use in a computer-assisted integrated design layout process, circuit entities are placed by a computer program on a layout of an integrated circuit stored in computer memory. The circuit to be laid out is represented in computer memory as circuit entities interconnected between pins on the circuit entities. A set of pins to be interconnected forms a net and is assigned a weight. The method allows a user to cause the computer program to place a circuit entity at a different location on the integrated circuit layout than it would otherwise. A faked two pin net is defined, one pin being located on the circuit entity and another pin being located in a region of the integrated circuit in which the user desires the circuit entity to be placed. A high weight is then assigned to the faked two pin net that is much greater than weights assigned to other nets in the integrated circuit layout. The computer program then places the circuit entity in the region of the other pin in accordance with the high weight assigned to the faked net.

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San Jose, CA, United States of America

Siu-Tong Hui