Marvell International Limited

Marvellworld Trade Ltd.

Siu-Hung Frederick Au

Fei Sun

Hyunsuk Shin

Chi Kong Lee

ChengKuo Huang

Wei Xu

Jungil Park

Jinjin He

Perry Neos

Lau Nguyen

Bo Fu

Chih-Ching Chen

Cheng Kuo Huang

Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs.

Architecture for storage of data on NAND flash memory

The present disclosure includes systems and techniques relating to management of bit line errors based on a stored set of data. In some implementations, a system can include a device including non-volatile solid state memory and a memory controller. The memory controller can be configured to identify, from the solid state memory of the device, one or more bit line errors for the device upon power up of the system, construct a set of data corresponding to the one or more bit line errors for the device, store the set of data, at least in part, in the device, and, upon a subsequent power up of the system, identify the one or more bit line errors for the device from the stored set of data.

Management of bit line errors based on a stored set of data

A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.

Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive

The present disclosure includes systems and techniques relating to adjusting bit reliability information input for decoding data stored in a memory device. In some implementations, an apparatus, systems, or methods can include a memory controller that includes circuitry configured to receive data from a memory device, where the data includes at least first and second states; circuitry configured to compare a number of the first and second states of the received data; and circuitry configured to adjust a bit reliability information input to a decoder based, at least in part, on the comparison.

Adjusting bit reliability information input for decoding stored data

A memory device and method, such as a flash memory device and method, includes a memory having a plurality of nonvolatile memory cells for storing stored values of user data. The memory device and method includes a memory controller for controlling the memory. The memory controller includes an encoder for encoding user write data for storage of code values as the stored values in the memory. The encoder includes an inserter for insertion of an indicator as part of the stored values for use in determining when the stored values are or are not in an erased state. The memory controller includes a decoder for reading the stored values from the memory to form user read data values when the stored values are not in the erased state.

Method and apparatus for detecting valid data using selective modification of cyclic redundancy codes

Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page.

Architecture to allow efficient storage of data on NAND flash memory

A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and initiating transmission of the group of data units to the host in accordance with the first sequence.

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Fremont, CA, United States of America

Siu-Hung Frederick Au