Synopsys, Inc.

Sitikant Sahu

Parijat Biswas

Alexander John Wakefield

Pravash Chandra Dash

Sharad Nijhawan

Ractim Chakraborty

Manoharan Vellingiri

Rahul Garg

Minakshi Chakravorty

Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

Performing hardware description language transformations

Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second signal signature, designate the first signal as a master signal and designate the second signal as a slave signal; and stop dumping the second signal to a storage space.

Hardware simulation systems and methods for reducing signal dumping time and size by fast dynamical partial aliasing of signals having similar waveform

The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.

Graphical view and debug for coverage-point negative hint

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Bengaluru, India

Sitikant Sahu