Intel Corporation

Other

Sitaram Yadavalli

Leslie E Cline

Ishmael F Santos

Jim Hermerding

Tracy Garrett Drysdale

Sandip Kundu

Sanjay Sengupta

Husnara Khan

This application discloses a mechanism to securely store and compute with a matrix of numbers or any two-dimensional array of binary values in a storage entity called a matrix space. A matrix space is designed to store matrices or arrays of values into arrays of volatile or non-volatile memory cells with accessibility in two or three dimensions. Any row or column or line of storage elements in the storage entity is directly accessible for writing, reading, or clearing via row bit lines and column bit lines, respectively. The elements in rows of the arrays are selected or controlled for access using row address lines and the elements in columns of the arrays are selected or controlled for access using column address lines. Access control methods and mechanisms with keys to secure, share, lock, and unlock regions in the matrix space for matrices and arrays under the control of an operating system or a virtual-machine hypervisor by permitted threads and processes are also disclosed.

Computing machine with secure matrix space

Parallel instruction demarcators and methods for parallel instruction demarcation are included, wherein an instruction syllable sequence comprising a plurality of instruction syllables is received and stored at an instruction buffer. It is determined, using one or more logic blocks arranged in a sequence, a size of an instruction and at least one boundary at which the instruction is demarcated. Additionally, using a controlling logic block a restart point is determined from where the sequence of instruction syllables is examined and demarcated into individual instructions.

Parallel instruction demarcator

Secure matrix space with partitions for concurrent use

This disclosure relates to methods and mechanisms for matrix computing which include machine embodiments with one or more matrix storage spaces for holding matrices and arrays for computing, where a matrix or an array is accessible by its columns, by its rows, or both, individually, or concurrently. A set of methods and mechanisms to build a large capacity instruction set with multi-length instructions to load, store, and compute with these matrices and arrays are also disclosed. Methods and access control mechanisms with keys to secure, share, lock and unlock regions in the storage space for matrices and arrays under the control of an operating system or a virtual machine hypervisor by permitted threads and processes are also disclosed. Methods and mechanisms to handle long immediate operands for use by shorter instructions using a payload instruction are also disclosed. The structure of the instructions with key instruction fields and a method for determining instruction length are also disclosed.

Computing machine using a matrix space and matrix pointer registers for matrix and array processing

Instruction length based parallel instruction demarcators and methods for parallel instruction demarcation are included, wherein an instruction sequence is received at an instruction buffer, the instruction sequence comprising a plurality of instruction syllables, and the instruction sequence is stored at the instruction buffer. It is determined, using one or more logic blocks arranged in a sequence, a length of instructions and at least one boundary. Additionally, using a controlling logic block, the sequence is demarcated into individual instructions.

Instruction length based parallel instruction demarcator

This invention uses a novel mechanism to store a matrix of numbers or any two dimensional array of binary values in a novel storage entity called a Matrix Space. A matrix space which may reside in a processing unit, is designed to store a plurality of matrices or arrays of values into arrays of volatile or non-volatile memory cells or latch or flip-flop elements much like in a memory, but with accessibility in two or three dimensions. In this invention any row and/or any column of storage elements in a storage array is directly accessible for writing, reading or clearing via row bit lines and column bit lines, respectively. The elements in rows of arrays are selected or controlled for access using row address lines and the elements in columns of arrays are selected or controlled for access using column address lines. This allows access to data stored in matrix space arrays for use in matrix and array computations, by both rows and columns of the arrays.

Method and apparatus for storing and accessing matrices and arrays by columns and rows in a processing unit

For one disclosed embodiment, a lower limit for a power consumption device may be identified. Performance of the power consumption device may be reduced in response to a determination that a temperature corresponding to the power consumption device exceeds a threshold. Performance reduction may be limited based on the lower limit. Other embodiments are also disclosed.

Performance reduction limit for power consumption device

Methods and apparatuses for intervening in the self power or thermal regulations of a plurality of independent power consumption devices are described herein. The novel methods may include monitoring power consumption and thermal conditions of the plurality of power consumption (i.e., power/heat dissipation) devices that are configured to independently self-regulate their power/thermal production. A determination may then be made as to whether an aggregate of the power and/or thermal production of the plurality of power consumption devices exceed a threshold. And if the aggregate of the power or thermal production of the power consumption devices was determined to exceed the threshold, terminating, at least partially, the independent self-regulating of the thermal production and intervening in the thermal regulation of one or more of the power consumption devices. In contrast, if the aggregate of the power and/or thermal production of the plurality of power consumption devices is determined to be below the threshold then the power consumption devices may be allowed to self-regulate their power consumptions, and in some instances, one or more of the individual power clamps for the one or more of the power consumption devices may be relaxed or raised.

Intervention of independent self-regulation of power consumption devices

Various methods, apparatuses, and systems that use a replacement policy algorithm to implement tracking of one or more memory locations that have incurred one or more data transfer failures.

Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations

A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element.

Method and apparatus for modeling and circuits with asynchronous behavior

A technique for a scan design employing a register transfer level scan selection which requires that either all bits of a register are designated to have all scan or all non-scan properties. No separate elements (bits) of a register are selected for individual scan. By designating scan selection at the register level, register-transfer-level (RTL) specifications of a digital circuit can employ signal flow vectors at the register level and not at the conventional logic gate level. In one technique, a number of registers are grouped to have the same scan or non-scan property. Such grouping is used to provide a common template for inserting scan into multiple instantiated modules. The group designation for selecting scan or non-scan registers is also used to scan registers at the memory input, output, both input and output, or neither, which then can be used for testing memory devices.

Growing community of inventors

San Jose, CA, United States of America

Sitaram Yadavalli