Texas Instruments Corporation

Siraj Akhtar

Baher S Haroun

Swaminathan Sankaran

Petteri Matti Litmanen

Marco Corsi

Nirmal Chindhu Warke

Gerd Schuppener

Salvatore Luciano Finocchiaro

Richard Francis Taylor, Iii

Tolga Dinc

Srinath Hosur

Martin J Izzard

Robert Bogdan Staszewski

Timothy M Schmidl

Nikolaus Klemmer

Anant Shankar Kamath

Kumar Anurag Shrivastava

Himanshu Arora

Tolga Dine

Anand Ganesh Dabak

Andrew Marshall

Robert Floyd Payne

Khurram Waheed

Yiqi Tang

Srikanth Krishnan

Vijay Kumar Reddy

Mark Edward Wentroble

Rakesh Hariharan

Suvadip Banerjee

Hamid Safiri

Karan Singh Bhatia

Sylvester Ankamah-Kusi

Mehmet Ipek

Kishalay Datta

Wenjing Lu

Lu Sun

Diptendu Ghosh

Rr Manikandan

Gurumurti Kailaschandra Avhad

An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.

Electronic device and multilevel package substrate with integrated filter

In an example apparatus, a first transistor has a base terminal, a first current terminal and a second current terminal. The base terminal is coupled to an input voltage node. A second transistor has a control terminal, a third current terminal and a fourth current terminal. The third current terminal is coupled to the second current terminal. The fourth current terminal is coupled to a first resistor. A second resistor is coupled to the control terminal. An inductor is coupled between the first resistor and a ground terminal.

Methods and apparatus for voltage buffering

An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.

Methods and apparatus to reduce variations for on-off keying transmissions

In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

Self-calibrating on-off keying based digital isolator

A circuit includes a main amplifier having a first input and a first output. A main bias circuit is coupled to the main amplifier, and the main bias circuit configured to operate the main amplifier in a first frequency band. A feedforward cancellation amplifier has a second input and a second output, in which the second input is coupled to the first input, and the second output is coupled to the first output. A filter is coupled between the first input and the second input. A feedforward bias circuit is coupled to the feedforward cancellation amplifier. The feedforward bias circuit is configured to operate the feedforward cancellation amplifier in a second frequency band within and narrower than the first frequency band.

Amplifiers with feedforward cancellation

In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

Charge pump

In described examples, a method of operating a transceiver with a transmitter and a receiver includes generating a frequency reference. In the transmitter: A phase locked loop (PLL) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference. A VCO in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PLL is locked to the transmitter VCO signal. In the receiver: A signal is received. A receiver VCO generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90&#xb0; to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component.

Transceiver carrier frequency tuning

Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. In one embodiment, a networking device includes an input port circuit having a transmitter circuit coupled one or more transmitter antennas, wherein the input port circuit transmits a data packet to a first output port circuit using millimeter wave signals. The networking device includes output port circuits including at least the first output port circuit, each of the output port circuits having a receiver circuit coupled to one or more receiver antennas. The networking device includes a beamforming circuit coupled to the one or more transmitter antennas of the input port circuit, wherein the beamforming circuit causes the one or more transmitter antennas to transmit an antenna beam directed at the one or more receiver antennas of the first output port circuit.

Wireless chip-to-chip switching

Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

Methods and apparatus for phase imbalance correction

In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

Carrier frequency recovery in a receiver

In described examples of a magnetically coupled structure on a substrate with an integrated circuit device, the structure includes a first coil in a differential configuration, a second coil located above the first coil in a generally stacked configuration, and a center tap connection to a winding of the second coil. The first coil includes a first differential terminal, a second differential terminal, and metal windings of the first coil. The first coil's metal windings form a continuous spiral electrical path between the first and second differential terminals. The first coil's metal windings include turns and crossing connections between the turns. The turns are fabricated in an integrated circuit metal wiring level, and the crossing connections are fabricated in at least one metal level other than the metal wiring level containing the turns. The center tap is positioned to create a balanced structure.

Baluns for RF signal conversion and impedance matching

A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

PLL lock range extension over temperature

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Richardson, TX, United States of America

Siraj Akhtar