Intel Corporation

Sion Berkowits

Ali-Reza Adl-Tabatabai

Bratin Saha

Yang Ni

Ady Tal

Michael Berezalsky

Noam Itzhaki

Arik Narkis

Jeffrey V Olivier

James Henry Cownie

Moshe Maury Bach

Julia Fedorova

Anton V Gorshkov

Konstantin Levit-Gurevich

Orna Etzion

Adam Welc

Sunpyo Hong

Konstantin Levit-Guervich

Adam Wele

Li Jianhui

Aleksey Alekseev

Disclosed examples to perform instruction-level graphics processing unit (GPU) profiling based on binary instrumentation include: accessing, via a GPU driver executed by a processor, binary code generated by a GPU compiler based on application programming interface (API)-based code provided by an application; accessing, via the GPU driver executed by the processor, instrumented binary code, the instrumented binary code generated by a binary instrumentation module that inserts profiling instructions in the binary code based on an instrumentation schema provided by a profiling application; and providing, via the GPU driver executed by the processor, the instrumented binary code from the GPU driver to a GPU, the instrumented binary code structured to cause the GPU to collect and store profiling data in a memory based on the profiling instructions while executing the instrumented binary code.

Methods and apparatus to perform instruction-level graphics processing unit (GPU) profiling based on binary instrumentation

Systems, apparatuses and methods may provide for technology that receives compiled code and identifies a plurality of blocks in the compiled code. Instrumented code may be generated from the compiled code by modifying the blocks to include probes to measure latencies of the blocks during execution of the instrumented code on a graphics processing unit.

Latency measurement technology

A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system

A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at least one denormal exception of a faulty target instruction by executing the set of target instructions; assign a predetermined value to one or more denormal operands of the faulty target instruction; and execute the faulty target instruction with the predetermined value for the one or more denormal operands. An apparatus, system, and machine-readable medium may perform such methods.

Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism

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Haifa, Israel

Sion Berkowits