Fujitsu Corporation

Fujitsu Microcomputer Systems Limited

Sinji Nishikawa

Hiroyuki Fujiyama

Tetsuo Suzuki

Hidetoshi Shimura

Shinji Oyamada

Kouichi Kuroiwa

An interrupt processing method and an interrupt processing apparatus provides an end indicative information storing unit for storing an end indicative information of a daisy chain for at least one of a plurality peripheral units, the peripheral unit receiving the indicative information when the peripheral unit receives an acknowledge signal but does not output a request signal, and the peripheral unit outputs a specific chain end state signal to the central processing unit, so that the central processing unit is returned from a response waiting state. Therefore, when an error request signal is produced by noise, etc., delay at a central processing unit is reduced. Further, the daisy chain connection is cut at an optional portion and a request signal from an irrevelant peripheral unit is ignored, so that the efficiency of the processing is improved.

Method and apparatus for interrupt processing in a computer system

A register circuit comprises a plurality of registers commonly receiving a data signal and selection signals respectively, each of the registers including a first input terminal for receiving the data signal; a second input terminal for receiving a corresponding one of the selection signals; an output terminal for outputting a stored data signal; a storing unit, connected to the output terminal, for storing the data signal; and a control unit, connected to the storing unit, the first input terminal, the second input terminal, and the output terminal, for transferring the data signal to the storing unit when the selection signal is effective and resetting the storing unit when the data signal is already stored in the storing unit and the selection signal is not effective.

Register circuit with plural registers simultaneously reset when a

A microcomputer unit containing therein a plurality of registers each with an address allotted in advance. The registers can be accessed for monitoring by an external address signal when the allotted address thereof and the external address signal coincide with each other. In this case, operation of the microcomputer is stopped by an external HALT signal and then the content of the register to be monitored is read by a monitor (MNT) signal MNT, so that the content thereof is fed externally from the microcomputer unit.

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Kawasaki, Japan

Sinji Nishikawa