National Semiconductor Corporation

Texas Instruments Corporation

Sing W Chin

Michael K Mayes

Bumha Lee

Bill C Wong

Satoshi Sakurai

Hao Yu

Ion E Opris

David Brian Barkin

A high-speed unity-gain input buffer steers the current that flows down a first path to an output node, and down a second path in response to an analog input signal. The current that flows down the second path is mirrored to sink a current out of the output node.

High-speed unity-gain input buffer having improved linearity and stability with a low supply voltage

A duty cycle correction circuit () for receiving an input clock signal () and generating an output clock signal () having a predetermined duty cycle includes a clock trigger circuit () generating the output clock signal () having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (); a charge pump circuit () receiving the output clock signal and generating charging and discharging currents for a capacitor (C) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit () receiving the control voltage and generating first and second bias voltages () in response to the control voltage; and a delay-locked loop circuit () receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.

Duty cycle correction circuit with small duty error and wide frequency range

A reference voltage buffer circuit () includes first and second transistors (M, M) and first and second resistors (R, R) connected in series between positive and negative power supply voltages and providing a positive reference voltage (Vrp) and a negative reference voltage (Vrn) at the first current handling terminals of the first and second transistors, respectively. A first control voltage (Vg) for driving the first transistor is generated by a first feedback loop and using a positive boosted voltage. A second control voltage (Vg) for driving the second transistor is generated by a second feedback loop and using a negative boosted voltage. The first and second feedback loops establish the first and second control voltages while the positive and negative boosted voltages ensure sufficient drives are provided to the first and second transistors. The reference voltage buffer is capable of fast settling while maintaining a wide reference voltage range.

Fast settling reference voltage buffer with wide reference range

A gain-boosted telescopic amplifier () includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (M, M), a pair of NMOS gain-boosted cascode transistors (M, M) and a pair of PMOS gain-boosted cascode transistors (M, M). The amplifier includes first and second clamping circuits driving the gate terminals of the pair of PMOS cascode transistors, respectively. The clamping circuits limit the gate voltage of the PMOS cascode transistors to be within a threshold voltage from the desired bias voltage. Each clamping circuit can include only a pull-down device, a pull-up device or both. In another embodiment, the amplifier includes clamping circuits driving the gate terminals of the pair of NMOS cascode transistors for limiting the gate voltage of the NMOS cascode transistors to be within a threshold voltage of the desired bias voltage.

Bias device clamping circuit for fast over-range recovery

A duty cycle stabilizer circuit () receiving an input clock signal and generating an output clock signal having a first duty cycle includes a leading edge pulse generator () and a pulse width extender circuit (). The pulse generator generates a first clock pulse (V) having a leading edge triggered by the leading edge of the input clock signal and a first pulse width. The pulse width extender circuit generates a second clock pulse (V) having a leading edge triggered by the leading edge of the first clock pulse and a pulse width being stretched to the desired duty cycle. The duty cycle stabilizer further includes a buffer () providing the output clock signal having the first duty cycle, a charge pump () receiving the output clock signal directly and a differential amplifier () generating an output signal for controlling the pulse width of the first and second clock pulses.

Duty cycle stabilizer

Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.

Pipeline ADC using multiplying DAC and analog delay circuits

An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.

Algorithmic analog-to-digital converter with reduced differential

An n-bit analog-to-digital converter system, where n is a positive integer, includes a ratioed reference voltage generator that uses a reference voltage V.sub.ref. The reference voltage generator includes a voltage selector having a plurality of voltage selector inputs and a plurality of voltage selector outputs for applying a first voltage to a corresponding voltage selector output during a time period .phi..sub.1 and for applying a second voltage to a corresponding voltage selector output during a following time period .phi..sub.2. The voltage applied to one voltage selector output during any time period is not necessarily the same as the voltage applied to another voltage selector output. The reference voltage generator further includes an amplifier having a plurality of inputs and a differential voltage output and a plurality of sets of capacitances. Each set of capacitances couples an associated one of the voltage selector outputs to an associated one of the inputs of the amplifier and has a value such that the electrical combination of the voltages and capacitances provides a voltage level of .+-.V.sub.ref /m, where m is any desired number, at the differential output of the amplifier.

N-bit analog-to-digital converter having ratioed reference voltage

A novel ratioed reference voltage circuit is taught which enables positive and negative output voltages as a ratio of a given reference voltage. The desired ratio is established by capacitor ratios. During the operation of the circuit, positive and negative ratioed output voltages are provided at various points in time which are not necessarily very accurate due to component mismatches and the like. However, the average of the positive ratioed reference voltage during two different periods of time is a highly accurate positive ratioed reference voltage due to error cancellation. Similarly, the average of the negative ratioed reference voltage during two different periods of time is a highly accurate negative ratioed reference voltage due to error cancellation.

Ratioed reference voltage generation using self-correcting capacitor

An ADC system in which raw ADC data is received and digitally manipulated to increase the accuracy of the resultant digital output word. In one embodiment, the digital manipulation of this invention is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correction is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance. In accordance with one embodiment of this invention, offset error and full scale error are determined by applying .+-.Vref as an input signal to the ADC. These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital representation of the analog input voltage being measured. In accordance with another embodiment of this invention, second order errors are removed by determining the magnitude of, for example, capacitor value voltage coefficients of the MSB stage of the ADC after calibration of lesser significant bit stages, and using these voltage coefficients to further adjust the digital output word, providing an even more accurate digital representation of the analog input signal being measured.

Pipelined analog-to-digital converter with curvefit digital correction

An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a 'parallel successive approximation register' circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring reference voltages produced by the resistance ladder circuit, and cover a predefined range of voltages above and below the voltage associated with the ten-bit value generated during the first two conversion cycles. Then a voltage derived from the input voltage is compared with these generated voltages to generate a correction value that is combined with the ten-bit value generated during the initial conversion cycles to produce a 12-bit conversion value.

Multistep analog-to-digital converter with successive approximation

An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value. In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC's embedded memory, corresponding to the estimated conversion value from the first conversion cycle, thereby correcting for any non-uniformities in the resistances of the resistor ladder.

Multistep analog-to-digital converter with embedded correction data

A novel multistep flash analog to digital converter is taught, including a voltage estimator which quickly provides a rough estimate of the analog input signal. This rough estimate is used to select appropriate reference voltage tap points for use in the first flash conversion. This first flash conversion, together with the voltage estimate, provides the most significant bits of the digital output word. A digital to analog converter is used to provide a residual voltage which is then converted by a second operation of the flash converter, thereby providing the least significant bits of the digital output word. In one embodiment, the voltage estimate is performed at the same time that the analog input signal is sampled by the flash converter in preparation for the first flash conversion. Therefore, speed of operation is not degraded by the addition of the voltage estimator.

Multistep flash analog to digital converter with voltage estimator

A pair of CMOS inverters are cross coupled in a latching configuration. Both inverter supply terminals are coupled to complementary toggles that can render the inverters operative or inoperative. First, the inverters are rendered inoperative. An output switch is coupled between the output nodes so that the inverter's output nodes can be driven to the same potential, thus canceling any offset voltage. An input switch produces sampling over a time interval that extends beyond the output switch on period. After the sampling period, the toggles are operated to turn the inverters on and to produce a latch state determined by the potential change present in the sampling interval.

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Alameda, CA, United States of America

Sing W Chin